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UC3869G-S08-R 数据表(PDF) 6 Page - Unisonic Technologies

部件名 UC3869G-S08-R
功能描述  High voltage startup
PDF  8 Pages
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制造商  UTC [Unisonic Technologies]
网页  http://www.utc-ic.com
标志 UTC - Unisonic Technologies

UC3869G-S08-R 数据表(HTML) 6 Page - Unisonic Technologies

  UC3869G-S08-R Datasheet HTML 1Page - Unisonic Technologies UC3869G-S08-R Datasheet HTML 2Page - Unisonic Technologies UC3869G-S08-R Datasheet HTML 3Page - Unisonic Technologies UC3869G-S08-R Datasheet HTML 4Page - Unisonic Technologies UC3869G-S08-R Datasheet HTML 5Page - Unisonic Technologies UC3869G-S08-R Datasheet HTML 6Page - Unisonic Technologies UC3869G-S08-R Datasheet HTML 7Page - Unisonic Technologies UC3869G-S08-R Datasheet HTML 8Page - Unisonic Technologies  
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UC3869
Preliminary
CMOS IC
UNISONICTECHNOLOGIESCO.,LTD
6 of 8
www.unisonic.com.tw
QW-R103-110.c
OPERATION DESCRIPTION
The UTC UC3869 devices integrate many useful designs into one controller for low-power switch-mode power
supplies. The following descriptions highlight some of the features of the UTC UC3800 series.
Internal High Voltage Startup and Under Voltage Lockout (UVLO)
UTC UC3869 integrated HV start circuit, and provide about 0.25mA current to charge VDD pin during power on
state from HV pin. When VDD cap voltage is higher than UVLO(OFF), the charge current is switched off. At this
moment, the VDD capacitor provides current to UTC UC3869 until the auxiliary winding of the main transformer starts
to provide the operation current.
Operating Current
The typical operating current of UTC UC3869 is 0.8mA. Good efficiency is achieved with this low operating
current together with the ‘Extended burst mode’ control features.
Soft Start
UTC UC3869 features an internal 5ms soft start to soften the electrical stress occurring in the power supply
during startup. It is activated during the power on sequence. As soon as VDD reaches UVLO (OFF), the CS peak
voltage is gradually increased from 0V to the maximum level. Every restart up begins with a soft start.
Frequency shuffling for EMI improvement
The frequency shuffling (switching frequency modulation) is implemented in UTC UC3869. The oscillation
frequency is modulated so that the tone energy is spread out. The spread spectrum minimizes the conduction band
EMI and therefore eases the system design.
Power-Saving Mode Operation
The proprietary Power-Saving Mode function provides linearly decreasing the switching frequency under
light-load conditions for higher efficiency. The feedback voltage, which is sampled from the voltage feedback loop, is
taken as the reference. Once the feedback voltage dropped below the threshold voltage, the switching frequency
starts to decrease. This Power-Saving Mode function dramatically reduces power consumption under light-load
conditions. The 22KHz minimum frequency control also eliminates the audio noise at any loading conditions.
At zero load condition, the magnitude of power loss is in proportion to the number of switching events within a
fixed period of time. Reducing switching events leads to the reduction on the power loss and thus conserves the
energy. The UTC UC3869 enter burst mode at standby condition to minimize the switching loss and reduces the
standby power consumption. Power supplies using the UTC UC3869 can easily meet even the strictest regulations
regarding standby power consumption.
Oscillator Operation
The switching frequency is internally fixed at 65KHZ. No external frequency setting components are required for
PCB design simplification.
Current Sensing and Leading Edge Blanking
Cycle-by-Cycle current limiting is offered in UTC UC3869 current mode PWM control. The switching current is
detected by a sense resistor connected to the CS pin. An internal leading edge blanking circuit chops off the sensed
voltage spikes due to snubber diode reverse recovery and surge gate current of power MOSFET at initial internal
power MOSFET on state. The current limiting comparator is disabled and cannot turn off the internal power
MOSFET during the blanking period. The PWM duty cycle is determined by the current sense input voltage and the
FB input voltage.
Internal Synchronized Slope Compensation
Built-in slope compensation circuit adds voltage ramp onto the current sense input voltage for PWM generation.
This greatly improves the close loop stability at CCM and eliminates the sub-harmonic oscillation and thus reduces
the output ripple voltage.



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