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UD36061G-AG6-R 数据表(PDF) 3 Page - Unisonic Technologies |
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UD36061G-AG6-R 数据表(HTML) 3 Page - Unisonic Technologies |
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3 / 6 page ![]() UD36061 Preliminary CMOS IC UNISONICTECHNOLOGIESCO.,LTD 3 of 6 www.unisonic.com.tw QW-R103-120.a PIN CONFIGURATION PIN DESCRIPTION PIN NO. PIN NAME DESCRIPTION 1 BST High-Side Gate Drive Boost Input. BST supplies the drive for the high-side N-Channel MOSFET switch. Connect a 0.1μF or greater capacitor from SW to BST to power the high side switch. 2 GND Ground. 3 FB Feedback Input. FB senses the output voltage to regulate that voltage. Drive FB with a resistive voltage divider from the output voltage. The feedback threshold is 0.8V. 4 EN Enable Input. Pulling this pin below the specified threshold shuts the chip down. Pulling it above the specified threshold enables the chip. Floating this pin shuts the chip down. 5 VIN Power Input. IN supplies the power to the IC, as well as the step-down converter switches. Drive IN with a 3.3V to 36V power source. Bypass IN to GND with a suitably large capacitor to eliminate noise on the input to the IC. 6 SW Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter from SW to the output load. A low VF Schottky diode to ground is required closed to this pin to reduce switching spikes. BLOCK DIAGRAM 5 REFFERENCE UVLO LOGIC OSCILATOR 2MHz INTERNAL REGULATOR ISW ISW SS 0.8V 0.5ms SS SS FB VIN BST SW GND EN 1 6 4 3 2 |
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