LOAD will load the first byte of data. Auto Incrementing is

disabled on the falling edge of LOAD after ADDRDATA and

LHBYTE goes low.

Manual Addressing Mode

Cycle #

Load Falling Edge

Load Rising Edge

1

Enable Manual Addressing

Load Address m

2

Enable Lbyte Data Load

Load Lbyte m

3

Enable Hbyte Data Load

Load Hbyte m

4

Enable Manual Addressing

Load Address n

5

Enable Lbyte Data Load

Load Lbyte n

6

Enable Hbyte Data Load

Load Hbyte n

Auto Addressing Mode

Cycle #

Load Falling Edge

Load Rising Edge

1

Enable Auto Addressing

Load Start Address n

2

Enable Lbyte Data Load

Load Lbyte (n)

3

Enable Hbyte Data Load

Load Hbyte (n); Inc Counter

4

Enable Lbyte Data Load

Load Lbyte (n+1)

5

Enable Hbyte Data Load

Load Hbyte (n+1); Inc Counter

6

Enable Manual Addressing

Load Address

ADDRDEC LOGIC

The ADDRDEC logic decodes the current address and gen-

erates the enable signal for the appropriate register. The en-

able values for the registers and counters change on the fall-

ing edge of LOAD. Two types of ADDRDEC logic is enabled

by 2 pair of addresses, Addresses 22 or 54 (Vectored Re-

start logic) and Addresses 23 or 55 (Vectored Clear logic).

Loading these addresses will enable the appropriate logic

and put the part into either a Restart (all counter registers are

reinitialized with preprogrammed data) or Clear (all registers

are cleared to zero) state. Reloading the same ADDRDEC

address will not cause any change in the state of the part.

The outputs during these states are frozen and the internal

CLOCK is disabled. Clocking the part during a Vectored Re-

start or Vectored Clear state will have no effect on the part.

To resume operation in the new state, or disable the Vec-

tored

Restart

or

Vectored

Clear

state,

another

non-ADDRDEC address must be loaded. Operation will be-

gin in the new state on the rising edge of the non-ADDRDEC

load pulse. It is recommended that an unused address be

loaded following an ADDRDEC operation to prevent data

registers from accidentally being corrupted. The following

Addresses are used by the device.

Address 0

Status Register REG0

Address 1–18Data Registers REG1–REG18

DS100232-7

DS100232-8

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