TLF9780

June 1989

5497DM7497

Synchronous Modulo-64 Bit Rate Multiplier

General Description

The ’97 contains a synchronous 6-stage binary counter and

six decoding gates that serve to gate the clock through to

the output at a sub-multiple of the input frequency The out-

put pulse rate relative to the clock frequency is determined

by signals applied to the Select (S0 – S5) inputs Both true

and complement outputs are available along with an enable

input for each A Count Enable input and a Terminal Count

output are provided for cascading two or more packages

An asynchronous Master Reset input prevents counting and

resets the counter

Connection Diagram

Dual-In-Line Package

TLF9780 – 1

Order Number 5497DMQB 5497FMQB or DM7497N

See NS Package Number J16A N16E or W16A

Logic Symbol

TLF9780 – 2

Pin Names

Description

S0 – S5

Rate Select Inputs

CE

Count Enable Input (Active LOW)

CP

Clock Pulse Input (Active Rising Edge)

MR

Asynchronous Master Reset Input (Active HIGH)

Gated Clock Output (Active LOW)

Complement Output (Active HIGH)

TC

Terminal Count Output (Active LOW)

C1995 National Semiconductor Corporation

RRD-B30M115Printed in U S A