Application Information

SPI PIN DESCRIPTION

DATA: This is the serial data input pin.

CLK: This is the clock input pin.

ENB: This is the SPI enable pin and is active-high.

SPI OPERATION DESCRIPTION

The serial data bits are organized into a field which contains

8 bits of data defined by TABLE 1. The Data 0 to Data 2 bits

determine the output mode of the LM4851 as shown in

TABLE 2. The Data 3 to Data 7 bits determine the volume

level setting as illustrated by TABLE 3. For each SPI transfer,

the data bits are written to the DATA pin with the least

significant bit (LSB) first. All serial data are sampled at the

rising edge of the CLK signal. Once all the data bits have

been sampled, ENB transitions from logic-high to logic-low

to complete the SPI sequence. All 8 bits must be received

before any data latch can occur. Any excess CLK and DATA

transitions will be ignored after the eighth rising clock edge

has occurred. For any data sequence longer than 8 bits, only

the first 8 bits will get loaded into the shift register and the

rest of the bits will be disregarded.

TABLE 1. Bit Allocation

Data 0

Mode 1

Data 1

Mode 2

Data 2

Mode 3

Data 3

Volume 1

Data 4

Volume 2

Data 5

Volume 3

Data 6

Volume 4

Data 7

Volume 5

TABLE 2. Output Mode Selection

Output Mode #

Data 2

Data 1

Data 0

SPKR

OUT

R

OUT

L

OUT

0

0

0

0

SD

SD

SD

1

0

0

1

6dB x P

SD

SD

2

010

SD

P

P

3

0

1

1

G(R+L)

SD

SD

4

1

0

0

SD

GxR

GxL

5

1

0

1

G(R+L) + 6dB x P

SD

SD

6

1

1

0

SD

(GxR)+P

(GxL)+P

7

1

1

1

6dBxP

(GxR)+P

(GxL)+P

P = Phone In

R = Rin

L = Lin

SD = Shutdown

G = Gain of volume control

Default Mode upon device power-up is Output Mode 0

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