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[v1-00] 2016-Dec-16

AS7262 − Detailed Description

UART Interface

If selected by the I²C_ENB pin setting, the UART module

implements the TX and RX signals as defined in the RS-232 /

V.24 standard communication protocol.

It has on both, receive and transmit path, a 16 entry deep FIFO.

It can generate interrupts as required.

UART Feature List1

• Full Duplex Operation (Independent Serial Receive and

Transmit Registers) with FIFO buffer of 8 byte for each.

• At a clock rate of 16MHz it supports communication at

115200 Baud.

• Supports Serial Frames with 8 Data Bits, no Parity and 1

Stop Bit

Theory of Operation

Transmission

If data is available in the transmit FIFO, it will be moved into the

output shift register and the data will be transmitted at the

configured Baud Rate, starting with a Start Bit (logic zero) and

followed by a Stop Bit (logic one).

Reception

At any time, with the receiver being idle, if a falling edge of a

start bit is detected on the input, a byte will be received and

stored in the receive FIFO. The following Stop Bit will be checked

to be logic one.

Figure 29:

UART Protocol

1. With UART operation, min VDD of 2.97V is required as shown in Electrical Characteristics Figures.

Start Bit

Tbit=1/Baude Rate

Stop Bit

Next Start

Sample Points

Start Bit detected

After Tbit/2: Sampling of Start Bit

After Tbit: Sampling of Data

Always Low

Always High

Data Bits

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