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UTRS3080G-S08-R 数据表(PDF) 6 Page - Unisonic Technologies

部件名 UTRS3080G-S08-R
功能描述  CMOS IC
PDF  9 Pages
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制造商  UTC [Unisonic Technologies]
网页  http://www.utc-ic.com
标志 UTC - Unisonic Technologies

UTRS3080G-S08-R 数据表(HTML) 6 Page - Unisonic Technologies

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UTRS3080
Preliminary
CMOS IC
UNISONICTECHNOLOGIESCO.,LTD
6 of 9
www.unisonic.com.tw
QW-R113-017.b
SWITCHING CHARACTERISTICS
(VCC=+5.0V ±5%, TA=TMIN to TMAX, unless otherwise noted. Typical values are at VCC=+5.0V and TA=+25°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
UNIT
tDPLH
100
ns
Driver Input to Output
tDPHL
Fig.3 and 5, RDIFF=54Ω, CL1=CL2=100pF
100
ns
Driver Output Skew
| tDPLH - tDPHL |
tDSKEW Fig.3 and 5, RDIFF=54Ω, CL1=CL2=100pF
5
200
ns
Driver Rise or Fall Time
tDR, tDF Fig.3 and 5, RDIFF=54Ω, CL1=CL2=100pF
200
ns
Maximum Data Rate
fMAX
500
kbps
Driver Enable to Output High
tDZH
Fig.4 and 6, CL=100pF, S2 Closed
3500
ns
Driver Enable to Output Low
tDZL
Fig.4 and 6, CL=100pF, S1 Closed
3500
ns
Driver Disable Time from Low
tDLZ
Fig.4 and 6, CL=15pF, S1 Closed
200
ns
Driver Disable Time from High
tDHZ
Fig.4 and 6, CL=15pF, S2 Closed
200
ns
Receiver Input to Output
tRPLH,
tRPHL
Fig.7 and 9, |VID|≥2.0V; Rise and Fall Time
of VID≤15ns
200
ns
|tRPLH - tRPHL| Differential
Receiver Skew
tRSKD
Fig.7 and 9, |VID|≥2.0V; Rise and Fall Time
of VID≤15ns
50
ns
Receiver Enable to Output Low
tRZL
Fig.2 and 8, CL=100pF, S1 Closed
50
ns
Receiver Enable to Output High
tRZH
Fig.2 and 8, CL=100pF, S2 Closed
50
ns
Receiver Disable Time from Low
tRLZ
Fig.2 and 8, CL=100pF, S1 Closed
50
ns
Receiver Disable Time from
High
tRHZ
Fig.2 and 8, CL=100pF, S2 Closed
50
ns
Time to Shutdown
tSHDN
Note 1
200
ns
Driver Enable from Shutdown to
Output High
tDZH(SHDN) Fig. 4 and 6, CL=15pF, S2 Closed
4500
ns
Driver Enable from Shutdown to
Output Low
tDZL(SHDN) Fig.4 and 6, CL=15pF, S1 Closed
4500
ns
Receiver Enable from Shutdown
to Output High
tRZH(SHDN) Fig.4 and 6, CL=100pF, S2 Closed
3500
ns
Receiver Enable from Shutdown
to Output Low
tRZL(SHDN) Fig. 4 and 6, CL=100pF, S1 Closed
3500
ns
Note: The device is put into shutdown by bringing RE high and DE low. If the enable inputs are in this state for less
than 50ns, the device is guaranteed not to enter shutdown. If the enable inputs are in this state for at least
600ns, the device is guaranteed to have entered shutdown.



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