UU9792

Preliminary

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

6 of 15

www.unisonic.com.tw

QW-R125-047.a



FUNCTION DESCRIPTIONS (Cont.)

Command transfer method

Issue the Slave Address (01111100) after the start condition is generated.

Command input follows after the Slave Address. The least significant bit (LSB) of the Slave Address

determines if the operation to be done is Write or Read operation.

The MSB (command or data judgment bit) defines if the succeeding byte is a command or data.

When “Command or data judgment bit”= ‘1’, the next byte is a command.

When “Command or data judgment bit”= ‘0’, the next byte is display data.

S

Slave address

A

1 Command

A

1 Command

A

0 Command

A Display

… P

Once it enters display data transfer condition, it cannot input any command.

To input command again, please generate the “START condition” again.

If “START condition” or “STOP condition” is inputted in the middle of command transmission, the command will

be cancelled. If the Slave address is continuously inputted following “START condition”, it will be in command

input condition.

Please input “Slave Address” in the first data transmission after “START condition”.

When Slave Address cannot be recognized in the first data transmission, Acknowledge does not return and the

next transmission will be invalid. When data transmission is in invalid status and the “START condition” is

transmitted again, it will return to valid status.

Write display and transfer method

This device has Display Data RAM(DDRAM)of 20×4=80bit.

The relationship between data input and display data, DDRAM data and address are as follows.

S

0 1 1 1 1 1 0

A

Slave address

Command

0

0000000

Display Data

A

a b c d e f g h

A

P

I j k l m n o p

A

…

The 8-bit display data will be stored in the DDRAM. The address to be written is the address specified by

Address Set command, and the address is automatically incremented after every 4-bit of data.

Data can be continuously written in the DDRAM by transmitting Data continuously.

As data transfer to DDRAM is done every 4-bit data.

So it will be finished to transfer with no need to wait ACK.