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P12C508 数据表(PDF) 13 Page - Microchip Technology |
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P12C508 数据表(HTML) 13 Page - Microchip Technology |
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13 / 84 page ![]() © 1996 Microchip Technology Inc. Advance Information DS40139A-page 13 PIC12C5XX 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The special registers can be classified into two sets. The special function registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on MCLR and WDT Reset Value on Wake-up on Pin Change N/A TRIS I/O control registers --11 1111 --11 1111 --11 1111 N/A OPTION Contains control bits to configure Timer0, Timer0/WDT prescaler, interrupt on change, and weak pull-ups 1111 1111 1111 1111 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu uuuu uuuu 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu uuuu uuuu 02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111 1111 1111 03h STATUS GPWUF — PA0 TO PD ZDC C 0001 1xxx 000q quuu 100q quuu 04h FSR (12C508) Indirect data memory address pointer 111x xxxx 111u uuuu 111u uuuu 04h FSR (12C509) Indirect data memory address pointer 110x xxxx 11uu uuuu 11uu uuuu 04h FSR Indirect data memory address pointer 1xxx xxxx 1uuu uuuu 1uuu uuuu 05h OSCCAL CAL7 CAL6 CAL5 CAL4 — — — — 0111 ---- uuuu ---- uuuu ---- 06h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu --uu uuuu Legend: Shaded boxes = unimplemented or unused, — = unimplemented, read as '0' (if applicable) x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5 for an explanation of how to access these bits. |
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