LM555CM datasheet(10/12 Pages) NSC

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Applications Information (Continued)

50% DUTY CYCLE OSCILLATOR

For a 50% duty cycle, the resistors R

A and RB may be

connected as in Figure 14. The time period for the output

high is the same as previous, t

1 = 0.693 RA C. For the output

low it is t

2 =

Thus the frequency of oscillation is

Note that this circuit will not oscillate if R

B is greater than 1/2

A because the junction of RA and RB cannot bring pin 2

down to 1/3 V

CC and trigger the lower comparator.

ADDITIONAL INFORMATION

Adequate power supply bypassing is necessary to protect

associated circuitry. Minimum recommended is 0.1µF in par-

allel with 1µF electrolytic.

Lower comparator storage time can be as long as 10µs

when pin 2 is driven fully to ground for triggering. This limits

the monostable pulse width to 10µs minimum.

Delay time reset to output is 0.47µs typical. Minimum reset

pulse width must be 0.3µs, typical.

Pin 7 current switches within 30ns of the output (pin 3)

voltage.

00785117

VCC = 5V

Top Trace: Input 3V/Div.

TIME = 20µs/DIV.

Middle Trace: Output 5V/Div.

R1 = 47kΩ

Bottom Trace: Capacitor Voltage 1V/Div.

R2 = 100kΩ

RE = 2.7 kΩ

C = 0.01 µF

FIGURE 13. Linear Ramp

00785118

FIGURE 14. 50% Duty Cycle Oscillator

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