1–5

1.5

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

VCC

10,39,62

—

Power supply input, 3.3 V typical

VDD18†

37

1.8-V. When VREN is low, 1.8 V must be applied to provide current for the core during suspend.

VREN

38

I

Voltage regulator enable: enable active LOW; disable active HIGH

X2

60

O

12-MHz crystal output

X1

61

I

12-MHz crystal input

† During normal operation, the internal 3.3- to 1.8-V voltage regulator of the TUSB2136 is enabled and provides power to the core. To save power

during the suspend mode, the internal regulator is disabled. In this case, the pin becomes an input, and a simple external power source is required

to provide power to the core. This source needs to supply a very limited amount of power (10

µA maximum) within the voltage range of 1 to 1.95V.

NOTE 1: The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two

clock cycles and then the output is placed in a high-impedance state.

TEST0

TEST1

FUNCTION

0

0

Selects 48-MHz clock input (from an oscillator or other onboard clock source)

0

1

Reserved for testing purposes

1

0

Reserved for testing purposes

1

1

Selects 12-MHz crystal as clock source (default)