Data Sheet

ADL5904

Rev. 0 | Page 9 of 27

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

12

11

10

1

3

4

9

2

NOTES

1. DNC = DO NOT CONNECT.

2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW

IMPEDANCE THERMAL AND ELECTRICAL GROUND PLANE.

RFIN

DNC

VCAL

DECL

Q

GND

VRMS

CRMS

ADL5904

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

RFIN

RF Input. The RFIN pin is dc-coupled and is not internally matched. A broadband 50 Ω match is achieved using

an external 82.5 Ω shunt resistor with a 0.47 μF ac coupling capacitor placed between the shunt resistor and

the RF input. Smaller ac coupling capacitor values can be used if low frequency operation is not required.

2, 6, 8

DNC

Do Not Connect. Do not connect to these pins.

3

VCAL

Threshold Calibration. The voltage on this pin determines the correct threshold voltage that must be applied to

Pin 16 (VIN−) to set a particular RF power threshold. This process has two steps: first, measure the output

voltage on VCAL with no RF signal applied to RFIN (this voltage is typically 750 mV). Next, apply the RF input

power to RFIN, which causes the circuit to trip and again measure the voltage on the VCAL pin. The difference

between these two voltages is equal to the threshold voltage that must be applied to VIN− during operation.

4

DECL

Internal Decoupling. Bypass this pin to ground using a 4.02 Ω resistor connected in series with a 100 nF

capacitor.

5, 7

VPOS

The supply voltage range = 3.3 V ±10%. Place power supply decoupling capacitors on Pin 5. There is no

requirement for power supply decoupling caps on Pin 7.

9

CRMS

RMS Averaging Capacitor. Connect a capacitor between the DECL pin and the CRMS pin to set the appropriate

level of rms averaging. Set the value of the rms averaging capacitor based on the peak to average ratio and

bandwidth of the input signal and based on the desired output response time and residual output noise.

10

VRMS

RMS Detector Output. The output from the VRMS pin is proportional to the logarithm of the rms value at the

input level.

11

GND

Device Ground. Connect the GND pin to system ground using a low impedance path.

12, 13

Q, Q

Differential Digital Outputs of Threshold Detect Flip Flop. Q latches high when the output of the internal

envelope detector exceeds the threshold voltage on the internal comparator VIN− input.

14

ENBL

Device Enable. Connect the ENBL pin to logic high to enable the device.

15

RST

Flip Flop Reset. Taking RST high clears the latched flip flop output, setting the Q and Q outputs to low and high,

respectively.

16

VIN−

Inverting Input to the Threshold Detection Comparator. The voltage on this pin is compared to the output

voltage of the internal envelope detector, which is driven by the RF input level. If the output voltage of the

envelope detector exceeds the voltage on VIN−, the flip flop latches the Q output to high and the Q output to

low.

EPAD

Exposed Pad. Connect the exposed pad to a low impedance thermal and electrical ground plane.