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AD8223ARZ-R71 数据表(PDF) 16 Page - Analog Devices |
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AD8223ARZ-R71 数据表(HTML) 16 Page - Analog Devices |
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16 / 21 page ![]() AD8223 Rev. 0 | Page 15 of 20 REFERENCE TERMINAL The output voltage of the AD8223 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to level- shift the output so that the AD8223 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or −VS by more than 0.3 V. For best performance, keep the source impedance to the REF terminal below 5 Ω. As shown in Figure 31, the reference terminal, REF, is at one end of a 50 kΩ resistor. Additional impedance at the REF terminal adds to this resistor and results in poorer CMRR performance. INCORRECT AD8223 VREF CORRECT AD8223 OP2177 + – VREF Figure 32. Driving the Reference Pin INPUT PROTECTION Internal supply referenced clamping diodes allow the input, reference, output, and gain terminals of the AD8223 to safely withstand overvoltages of 0.3 V above or below the supplies. This is true for all gains, and for power-on and power-off. This last case is particularly important because the signal source and amplifier can be powered separately. If the overvoltage is expected to exceed this value, limit the current through these diodes to about 10 mA using external current limiting resistors. This is shown in Figure 33. The size of this resistor is defined by the supply voltage and the required overvoltage protection. 10mA 1 = 10mA MAX OUT AD8223 + – VOVER – VS + 0.7V +VS –VS RG RLIM RLIM RLIM = VOVER VOVER Figure 33. Input Protection RF INTERFERENCE (RFI) RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass, R-C network placed at the input of the instrumentation amplifier, as shown in Figure 34. The filter limits the input signal bandwidth according to the follow- ing relationship: ) (2 2 1 C D Diff C C R FilterFreq C CM RC FilterFreq 2 1 where CD ≥ 10CC. R R AD8223 +15V +IN –IN 0.1µF 10µF 10µF 0.1µF REF VOUT –15V R1 499Ω CD 47nF CC 1nF CC 1nF 4.02kΩ 4.02kΩ + – + Figure 34. RFI Suppression Figure 34 shows an example in which the differential filter fre- quency is approximately 400 Hz, and the common-mode filter frequency is approximately 40 kHz. The typical dc offset shift over frequency is less than 1.5 μV, and the RF signal rejection of the circuit is better than 71 dB. The resistors were selected to be large enough to isolate the circuit input from the capacitors but not large enough to significantly increase the circuit noise. Choose values of R and CC to minimize RFI. Mismatch between the R × CC at positive input and the R × CC at negative input degrades the CMRR of the AD8223. Because of their higher accuracy and stability, COG/NPO type ceramic capacitors are recommended for the CC capacitors. The dielectric for the CD capacitor is not as critical. |
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