AD8476

Data Sheet

Rev. B | Page 20 of 24

LOW POWER ADC DRIVING

The AD8476 is designed to be a low power driver for ADCs

with up to 16-bit precision and sampling rates of up to

250 kSPS. The circuit in Figure 56 shows the AD8476 driving

the AD7687, a 16-bit, 250 kSPS fully differential SAR ADC.

The filter between the AD8476 and the ADC reduces high

frequency noise and reduces switching transients from the

sampling of the ADC.

Choose the values of this filter with care. Optimal values for the

filter may need to be determined empirically, but the guidelines

discussed herein are provided to help the user. For optimum

performance, this filter should be fast enough to settle full-scale

to 0.5 LSB of the ADC within the acquisition time specified in

the ADC data sheet, in this case, the AD7687. If the filter is

slower than the acquisition time, distortion can result that looks

like harmonics. If the filter is too fast, the noise bandwidth of

the amplifier increases, thereby reducing the SNR of your

system.

Additional considerations help determine the values of the

individual components. THD of the ADC is likely to increase

with source resistance. This is stated in the ADC data sheet.

To reduce this effect, try to use smaller resistance and larger

capacitance. Large capacitance values much greater than 2 nF

are hard for the amplifier to drive. Higher capacitance also

increases the effect of changes in output impedance.

It is also important to consider the signal frequency range of

interest. The AD8476 THD decreases with higher frequency

(see Figure 42) and output impedance increases with higher

frequency (see Figure 49). This higher output impedance yields

slower settling, thus be certain to choose your capacitance so

that the filter still meets the settling requirement at the

maximum frequency of interest.

In the application shown, a 100 Ω resistors and 2.2 nF

capacitors at each output were chosen. For driving the AD7687,

this combination yields an SNR loss of 2.5 dB and good THD

performance for a 20 kHz fundamental frequency, with an ADC

throughput rate of 250kSPS. The filter bandwidth can be

determined by the following equation:

RC

Frequency

Filter



2

1



0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–180

–170

–160

–150

0

20406080

100

120

140

FREQUENCY (kHz)

THD = –112dB

SNR = 93dB

Figure 55. FFT of AD8476 Driving the AD7687

AD8476

AD7687

–OUT

+OUT

+IN

–IN

VOCM

+5V

VDD

IN–

IN+

+2.5V

+1.8V TO +5V

+5V

REF

GND

VIO

SDI

SCK

SDO

CNV

100Ω

100Ω

2.2nF

2.2nF

+4.5V

+2.5V

+0.5V

4V

+4V

+2V

0V

4V

+4V

+2V

0V

4V

+4.5V

+2.5V

+0.5V

4V

Figure 56. AD8476 Conditioning and Level Shifting a Differential Voltage to Drive Single-Supply ADC