AD8557ACPZ-R2 datasheet(15/25 Pages) AD

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AD8557

Data Sheet

Rev. D | Page 14 of 24

THEORY OF OPERATION

A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the

differential amplifier. A1 and A2 are auto-zeroed op amps that

minimize input offset errors. P1 and P2 are digital potentiome-

ters, guaranteed to be monotonic. Programming P1 and P2

allows the first stage gain to be varied from 2.8 to 5.2 with 7-bit

resolution (see Table 6 and Equation 1), giving a fine gain

adjustment resolution of 0.49%. Because R1, R2, R3, P1, and P2

each have a similar temperature coefficient, the first stage gain

temperature coefficient is lower than 100 ppm/°C.





























2.8

5.2

Code

GAIN1

(1)

A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of the

differential amplifier. A3 is an auto-zeroed op amp that mini-

mizes input offset errors and also includes an output buffer. P3

and P4 are digital potentiometers, which allow the second stage

gain to be varied from 10 to 250 in eight steps (see Table 7). R4,

R5, R6, R7, P3, and P4 each have a similar temperature coefficient,

so the second stage gain temperature coefficient is lower than

100 ppm/°C. The output stage of A3 is supplied from a buffered

version of VCLAMP instead of VDD, allowing the positive

swing to be limited.

A4 implements a voltage buffer, which provides the positive

supply to the output stage of A3. Its function is to limit VOUT

to a maximum value, useful for driving analog-to-digital

converters (ADC) operating on supply voltages lower than

VDD. The input to A4, VCLAMP, has a very high input

resistance. It should be connected to a known voltage and not

be left floating. However, the high input impedance allows the

clamp voltage to be set using a high impedance source, such as a

potential divider. If the maximum value of VOUT does not

need to be limited, VCLAMP should be connected to VDD.

An 8-bit digital-to-analog converter (DAC) is used to generate a

variable offset for the amplifier output. This DAC is guaranteed

to be monotonic. To preserve the ratiometric nature of the input

signal, the DAC references are driven from VSS and VDD, and

the DAC output can swing from VSS (Code 0) to VDD (Code

255). The 8-bit resolution is equivalent to 0.39% of the difference

between VDD and VSS, for example, 19.5 mV with a 5 V supply.

The DAC output voltage (VDAC) is given approximately by

 VSS

VSS

VDD

Code

VDAC





















256

(2)

where the temperature coefficient of VDAC is lower than

200 ppm/°C.

The amplifier output voltage (VOUT) is given by



 VDAC

VNEG

VPOS

GAIN

VOUT







(3)

where GAIN is the product of the first and second stage gains.

VDD

DIGIN

VSS

VDD

VSS

VDD

VCLAMP

VPOS

VSS

VOUT

VDD

VSS

VNEG

Figure 45. Functional Schematic

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