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P80C32 数据表(PDF) 13 Page - TEMIC Semiconductors |
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P80C32 数据表(HTML) 13 Page - TEMIC Semiconductors |
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13 / 20 page ![]() 80C32/80C52 Rev. G (14 Jan. 97) 13 MATRA MHS Absolute Maximum Ratings* Ambient Temperature Under Bias : C = Commercial 0 °C to 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I = Industrial -40 to 85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature –65 °C to + 150°C . . . . . . . . . . . . . . . . . . . . . . . Voltage on VCC to VSS –0.5 V to + 7 V . . . . . . . . . . . . . . . . . . . . . . . . Voltage on Any Pin to VSS –0.5 V to VCC + 0.5 V . . . . . . . . . . . . . . . Power Dissipation 1 W** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ** This value is based on the maximum allowable die temperature and the thermal resistance of the package * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Characteristics TA = 0 °C to 70°C ; Vcc = 2.7 V to 5.5 V ; Vss = 0 V ; F = 0 to 16 MHz TA = –40 °C to 85°C ; Vcc = 2.7 V to 5.5 V SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS VIL Input Low Voltage – 0.5 0.2 VCC – 0.1 V VIH Input High Voltage (Except XTAL and RST) 0.2 VCC + 1.4 VCC + 0.5 V VIH2 Input High Voltage to RST for Reset 0.7 VCC VCC + 0.5 V VIH1 Input High Voltage to XTAL1 0.7 VCC VCC + 0.5 V VPD Power Down Voltage to Vcc in PD Mode 2.0 5.5 V VOL Output Low Voltage (Ports 1, 2, 3) 0.45 V IOL = 0.8 mA (note 2) VOL1 Output Low Voltage Port 0, ALE, PSEN 0.45 V IOL = 1.6 mA (note 2) VOH Output High Voltage Ports 1, 2, 3 0.9 Vcc V IOH = – 10 µA VOH1 Output High Voltage (Port 0 in External Bus Mode), ALE, PSEN 0.9 Vcc V IOH = – 40 µA IIL Logical 0 Input Current Ports 1, 2, 3 – 50 µA Vin = 0.45 V ILI Input Leakage Current ± 10 µA 0.45 < Vin < VCC ITL Logical 1 to 0 Transition Current (Ports 1, 2, 3) – 650 µA Vin = 2.0 V IPD Power Down Current 50 µA VCC = 2.0 V to 5.5 V (note 1) RRST RST Pulldown Resistor 50 200 k Ω CIO Capacitance of I/O Buffer 10 pF fc = 1 MHz, TA = 25_C Maximum Icc (mA) OPERATING (NOTE 1) IDLE (NOTE 1) FREQUENCY/Vcc 2.7 V 3 V 3.3 V 5.5 V 2.7 V 3 V 3.3 V 5.5 V 1 MHz 0.8 mA 1 mA 1.1 mA 1.8 mA 400 µA 500 µA 600 µA 1 mA 6 MHz 4 mA 5 mA 6 mA 10 mA 1.5 mA 1.7 mA 2 mA 4 mA 12 MHz 8 mA 10 mA 12 mA 2.5 mA 3 mA 3.5 mA 16 MHz 10 mA 12 mA 14 mA 3 mA 3.8 mA 4.5 mA Freq > 12 MHz (Vcc = 5.5 V) Icc (mA) = 1.25 × Freq (MHz) + 5 Icc Idle (mA) = 0.36 × Freq (MHz) + 2.7 |
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