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ADA4077-2ARMZ-R7 数据表(PDF) 18 Page - Analog Devices |
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ADA4077-2ARMZ-R7 数据表(HTML) 18 Page - Analog Devices |
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18 / 25 page ![]() ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet Rev. D | Page 18 of 25 Figure 53. Small Signal Overshoot vs. Load Capacitance, VSY = ±5 V Figure 54. Positive 0.1% Settling Time, VSY = ±5 V Figure 55. Negative 0.1% Settling Time, VSY = ±5 V Figure 56. Small Signal Overshoot vs. Load Capacitance, VSY = ±15 V Figure 57. Positive 0.1% Settling Time, VSY = ±15 V Figure 58. Negative 0.1% Settling Time, VSY = ±15 V 0 5 10 15 20 25 30 35 40 1p 10p 100p 1n 10n LOAD CAPACITANCE (F) OS+ OS– VSY = ±5V RL = 2kΩ –0.03 –0.02 –0.01 0 0.01 0.02 0.03 0.04 0.05 TIME (1µs/DIV) VSY = ±5V VIN = 1V p-p RL = 2kΩ –0.03 –0.02 –0.01 0 0.01 0.02 0.03 0.04 0.05 VSY = ±5V VIN = 1V p-p RL = 2kΩ TIME (1µs/DIV) 0 5 10 15 20 25 30 35 40 1p 10p 100p 1n 10n LOAD CAPACITANCE (F) OS+ OS– VSY = ±15V RL = 2kΩ –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 0.25 VSY = ±15V VIN = 10V p-p RL = 2kΩ TIME (1µs/DIV) –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 0.25 VSY = ±15V VIN = 10V p-p RL = 2kΩ TIME (1µs/DIV) |
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