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LM70 数据表(PDF) 5 Page - National Semiconductor (TI) |
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LM70 数据表(HTML) 5 Page - National Semiconductor (TI) |
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5 / 13 page ![]() Logic Electrical Characteristics (Continued) SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS Unless otherwise noted, these specifications apply for V + = 2.65V to 3.6V for the LM70-3 and V+ = 4.5V to 5.5V for the LM70-5, C L (load capacitance) on output lines = 100 pF unless otherwise specified. Boldface limits apply for TA =TJ = T MIN to TMAX; all other limits TA =TJ = +25˚C, unless otherwise noted. Symbol Parameter Conditions Typical (Note 7) Limits (Note 8) Units (Limit) t 1 SC (Clock) Period 0.16 DC µs (min) (max) t 2 CS Low to SC (Clock) High Set-Up Time 100 ns (max) t 3 CS Low to Data Out (SO) Delay 70 ns (max) t 4 SC (Clock) Low to Data Out (SO) Delay 70 ns (max) t 5 CS High to Data Out (SO) TRI-STATE 200 ns (min) t 6 SC (Clock) High to Data In (SI) Hold Time 60 ns (min) t 7 Data In (SI) Set-Up Time to SC (Clock) High 30 ns (min) DS101223-4 FIGURE 2. Data Output Timing Diagram DS101223-5 FIGURE 3. TRI-STATE Data Output Timing Diagram DS101223-6 FIGURE 4. Data Input Timing Diagram www.national.com 5 |
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