HMC702LP6CE datasheet(21/38 Pages) AD

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HMC702LP6CE

v10.0812

14 GHz 16-BIT FRACTIONAL-N PLL

Nint

= 92

Nfrac

= 1

(EQ 14)

in this example the output frequency of 9,600,000,005.96 Hz is achieved by programming the 16-bit binary value of

92d = 5c = 0000 0000 0101 1100 into dsm_intg.

Similarly the 24-bit binary value of the fractional word is written into dsm_frac,

1d = 000 001h = 0000 0000 0000 0000 0000 0001

Example 2: Set the output to 12.600 025 GHz using a 100 MHz reference, r=2.

Find the nearest integer value, nint, nint = 126, fint = 12.600 000 GHz

this leaves the fractional part to be ffrac =25 kHz

(EQ 15)

Since Nfrac must be an integer number, the actual fractional frequency will be 24,998.19 Hz, an error of 1.81 Hz.

Here we program the 16-bit nint = 126d = 7Eh = 0000 0000 0111 1110 and

the 24-bit nfrac = 4194d = 1062h = 0000 0100 0001 0010

in addition to the above frequency programming words, the fractional mode must be enabled using the frac register.

other DSM configuration registers should be set to the recommended values. register setup files are available on

request.

Integer Frequency

the synthesizer is capable of operating in integer mode. in integer mode the digital Δ∑ modulator is normally shut

off and the division ratio of the Vco divider is set at a fixed value. to run in integer mode set dsm_integer_mode

(Reg12h<3> table 24) and clear dsm_rstb (Reg01h<13> table 7). then program the integer portion of the frequency,

NINT, as explained by (EQ 13), ignoring the fractional part.

Frequency Hopping Trigger

if the synthesizer is in fractional mode, a write to the fractional frequency register, Reg10h table 22, will initiate the

frequency hop on the falling edge of the 31st clock edge of the serial port write (see Figure 19).

if the integer frequency register, Reg0Fh table 21, is written when in fractional mode the information will be buffered

and only executed when the fractional frequency register is written.

if the synthesizer is in integer mode, a write to the integer frequency register, Reg0Fh table 21, will initiate the

frequency hop on the falling edge of the 31st clock edge of the serial port write (see Figure 19).

Power On Reset (POR)

normally all logic cells in the HMc702LP6cE are reset when the device digital power supply, DVDD, is applied. this

is referred to as Power on reset, or just Por. Por normally takes about 500us after the DVDD supply exceeds 1.5V,

guaranteed to be reset in 1msec. once the DVDD supply exceeds 1.5V, the Por will not reset the digital again unless

the supply drops below 100mV.

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rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

Phone: 781-329-4700 • Order online at www.analog.com

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