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MB91F577BHSPMC 数据表(PDF) 61 Page - Cypress Semiconductor

部件名 MB91F577BHSPMC
功能描述  32-bit RISC, load/store architecture, 5-stage pipeline
PDF  163 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

MB91F577BHSPMC 数据表(HTML) 61 Page - Cypress Semiconductor

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Document Number: 002-04725 Rev.*A
Page 61 of 163
MB91570 Series
11. I/O Map
The following I/O map shows the relationship between memory space and registers for peripheral resources.
Legend of I/O Map
The initial register value after reset indicates as follows:
"1": Initial value "1"
"0": Initial value "0"
"X": Initial value undefined
"-": Reserved bit/Undefined bit
"*": Initial value "0" or "1" according to the setting
Note:
It is prohibited to access addresses not described here.
000090H
BT1TMR[R] H
0000000000000000
BT1TMCR[R/W]B,H,W
00000000 00000000
000094H
BT1STC[R/W] B
00000000
000098H
BT1PCSR/BT1PRLL[R /W] H
0000000000000000
BT1PDU T/BT1PRLH/BT1D TBF[R/W] H
0000000000000000
00009CH
BTSEL[R /W] B
----000 0
BTSS SR[W] B,H
-------- ------11
0000A0 H
ADERH [R/W]B, H, W
00000000 00000000
ADER L [R/W]B, H, W
00000000 00000000
0000A4 H
ADC S1 [R/W] B, H,W
00000000
ADCS0 [R/W] B, H,W
00000000
ADCR1 [R] B, H,W
------XX
ADCR 0 [R] B, H,W
XXXXX XXX
0000A8 H
ADCT1 [R/W] B, H,W
00010000
ADC T0 [R/W] B, H,W
00101100
ADSCH [R/W] B, H,W
---00000
ADECH [R/W] B, H,W
---00000
+0
+1
+2
+3
Read/Write attribute (R: Read W: Write)
Data access attribute
B: Byte
H: Half-word
W: Word
(Note)
Initial register value after reset
Address
Address offset value/ register name
Block
Base timer 1
A/D converter
The access by the data access attribute
not described is disabled.



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