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MB91F577CSPMC 数据表(PDF) 56 Page - Cypress Semiconductor

部件名 MB91F577CSPMC
功能描述  32-bit RISC, load/store architecture, 5-stage pipeline
PDF  163 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

MB91F577CSPMC 数据表(HTML) 56 Page - Cypress Semiconductor

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Document Number: 002-04725 Rev.*A
Page 56 of 163
MB91570 Series
9. Block Diagram
Note: In this series, the HS-SPI function is prohibited
From Ma ste r
To Slave
From Ma ste r
To Slave
MD 0,MD 1,MD 2,P 12 7
WO T
NMIX
A DTG,A N0-39
A DC ena bled (A DER)
DA O0-1
RS TX
V0- 3,
ST 0- 8, CO M0- 3,
SEG 0- 31
SPI_CS0-3,
SPI_CLK,
SPI_SIO0-3
RX0-2,
TX0-2
A IN0-1,BIN0-1,Z IN0-1
SO T2-7,SIN2-7,
SCK2-7
Ex t-Bus Pins
D16-31,A 00-21,
A SX,CS0X,CS1X ,
RDX,W R0X,WR1X,
RDY ,SY SCLK
S O T 0/1/8/9,S IN 0/1/8/9,
S C K 0/1/8/9
OCU0-11
ICU0-11
FRCK0-5
INT0-15,
Hi-Z Controls f or
Standby Mode
SGO0-4,SGA 0-4
TIN0- 3,TOT0-3
TRG0-5,PPG0-23
PWM1M0-5,
PWM1P0-5,
PWM2M0-5,
PWM2P0-5
TIOA 0-1,TIOB0-1
XBS Crossbar Switch
FR81s CPU Core
Instr uc tion
D ata
Flash
・MainFlash ・WorkFlash 64KB
Ext-Bus I/F
Peripheral Bridge
CRC
Sound Generator (5ch)
16
32
CAN (3ch)
Wild Register
HS_SPI (1ch)
On-Chip Bus Layer 1
Debug Interface
Regulator
Power On Reset
CR OSC
NMI
Watchdog Timer (SW and HW)
Delayed Interrupt
Interrupt Controller
Reload Timer (4ch : ch.0,1,2,3)
PPG(24ch)
LCD Controller
Stepping Motor Controller (6ch)
AD Converter
Base Timer (2ch)
CAN Prescaler
RTC/WDT1 Calibration
Free Run Timer (6ch)
Lin-UART (6ch)
Input Capture (12ch)
Output Compare (12ch)
I/O Port Setting Registers
M ultif un c tion Serial Interf ac e (4c h)
Interrupt Requests Batch Reading
DMA Request and Clear MUX
External Interrupt Request (16ch)
RTC
Bus mats ter
DMAC
Register
Bus
Perf ormance
Counter
Mode Registers
RAM
Clock Controls (Configuration
Registers, Main Timer, Sub Timer,
PLL Timer)
M P U
Clock Controls (Divide Settings)
Reset Controls
Low Power Control Registers
Clock Bridge
(PCLK1⇔PCLK2)
Clock Bridge
(PCLK1⇔PCLK2)
Bus Bridge
( 32-bit ⇔ 16-bit)
Up Down Counter (2ch)
Low Voltage Detection (Internal Power Supply)
Reload Timer (3ch : ch.4,5,6)
Clock / Bus
Bridge
RAM ECC Control (XBS-RAM)
On-Chip Bus Layer 2
Clock Supervisor
DA Converter
RAM ECC
Control
Backup
-RAM
Low Voltage Detection (External Power Supply)



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