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MB91F577CSPMC 数据表(PDF) 101 Page - Cypress Semiconductor

部件名 MB91F577CSPMC
功能描述  32-bit RISC, load/store architecture, 5-stage pipeline
PDF  163 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

MB91F577CSPMC 数据表(HTML) 101 Page - Cypress Semiconductor

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Document Number: 002-04725 Rev.*A
Page 101 of 163
MB91570 Series
Address
Address offset value / Register name
Block
+0
+1
+2
+3
00FFF8H
EDIR1 [R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
00FFFCH
EDIR0 [R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
[S] : It is a system register. The illegal instruction exception (data access error) is generated when read/write is performed on these
registers in the user mode.
*3: The initial value is
different by part number. For details, refer to the CSVCR register in chapter “Clock Supervisor”
*4: MB91F578/9 only
*5: See the maximum size of series on the memory map



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