ZLED7010 datasheet(21/22 Pages) IDT

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ZLED7010 Datasheet

April 20, 2016

Layout Requirements

8.1.

Layout Considerations for ADJI (Pin 6)

For applications in which the ADJI pin is unconnected, minimize the length of circuit board traces connected to

ADJI to reduce noise coupling through this high impedance input.

8.2.

Layout Considerations for LX (Pin 8)

Minimize the length of circuit board traces connected to the LX pin because it is a fast switching output.

8.3.

Layout Considerations for VIN (Pin 1) and the External Decoupling Capacitor (C1)

The C1 input decoupling capacitor must be placed as close as possible to the VIN pin to minimize power supply

noise, which can reduce efficiency. See section 3.2 regarding capacitor selection.

8.4.

Layout Considerations for GND (Pin 7)

The ZLED7010 GND (ground) pin must be soldered directly to the circuit board’s ground plane to minimize

ground bounce due to fast switching of the LX pin.

8.5.

Layout Considerations for ADJO (Pin 5)

When the application requires a driver chain of multiple ZLED7010s, noise might be coupled in if there are longer

PCB traces from the driving ADJO pin to next stage ADJI pin. In this case, a 200pF (maximum) capacitor must be

connected between the line and ground to filter out the noise. The best practice is to connect one capacitor each

close to the ADJO output pin and the next stage ADJI input pins. The total capacitance in addition to the parasitic

capacitance from the ADJO pin to ground must not exceed 200pF. See Figure 5.1.

8.6.

Layout Considerations for RTH and RNTC (Pins 3 and 4)

The PCB trace from R2 to the RTH pin should be as short as possible to minimize noise coupling. Because the

NTC thermistor R3 is mounted close to the LEDs and remote from the ZLED7010, the PCB trace from R3 to RNTC

pin is longer and more susceptible to noise. A 100nF capacitor from the RNTC pin to ground and close to the RNTC

pin is recommended to filter the noise and provide protection against high voltage transients.

8.7.

Layout Considerations for High Voltage Traces

Avoid laying out any high voltage traces near the ADJ pin to minimize the risk of leakage in cases of board

contamination, which could raise the ADJ pin voltage resulting in unintentional output current. Leakage current

can be minimized by laying out a ground ring around the ADJ pin.

8.8.

Layout Considerations for the External Coil (L1)

The L1 coil must be placed as close as possible to the chip to minimize parasitic resistance and inductance,

which can reduce efficiency. The connection between the coil and the LX pin must be low resistance.

8.9.

Layout Considerations for the External Current Sense Resistor (RS)

Any trace resistance in series with RS must be taken into consideration when selecting the value for RS.

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