ZLED7015 datasheet(21/22 Pages) IDT

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ZLED7015 Datasheet

April 20, 2016

Layout Requirements

Follow these layout guidelines to avoid circuit instability and EMI vulnerability, especially with high current or high

switching frequency applications.

Important: Route traces connecting the feedback network to the FB and OVP pin away from the L1 inductor, the

D1 Schottky diode, and the LX pin. These traces should be as short as possible. Shield the FB pin and feedback

network with a ground plane or trace to prevent noise coupling.

7.1

General Considerations and Ground Traces

Make the ground traces as wide and short as possible. To prevent a signal ground shift, keep traces for the signal

ground (pin 5) separate from traces for the power ground (pin 1). Connect the signal and power ground traces

together at either the large ground plane or the negative terminal of CIN.

Connect the grounds for other components to the signal ground.

Use wide traces for connection of the high current loop.

7.2

Layout Considerations for C1, CIN, C2 and COUT

Place C1, C2 and COUT as close as possible to the ZLED7015 to minimize ripple. The CIN input decoupling

capacitor must be placed as close as possible to the VDD pin to minimize power supply noise, which can reduce

efficiency.

7.3

Layout Considerations for the EN Pin

Important: Do not allow the EN pin to float. It must be terminated if it is not used.

7.4

Layout Considerations for the LX Pin, L1 External Coil, and D1 Diode

Minimize the length of circuit board traces connected to the LX pin because it is a fast switching output.

Place L1 and D1 as close as possible to the LX pin using traces that are as short and wide as possible. Avoid

routing other traces crossing or in parallel with this node to minimize the noise coupling into this circuit.

7.5

Layout Considerations for the External Current Sense Resistor (RS)

Any trace resistance in series with RS must be taken into consideration when selecting its value. For the most

accurate LED current control, use a trace that is as wide and short as possible for the RS connection to ground.

Connect it to the signal ground (pin 5), not the power ground (pin 1).

7.6

Layout Considerations for CVP and CVDD

For good filtering, connect CVP as close as possible to the VP pin and place CVDD as close as possible to the VDD

pin.

7.7

Layout Considerations for the Thermal Pad

To optimize heat dissipation, solder the thermal pad on the back of the MSOP-10 package to the large ground

plan.

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