| 数据搜索系统,热门电子元器件搜索 |
|
ADA4522-2ARMZ-R7 数据表(PDF) 20 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADA4522-2ARMZ-R7 数据表(HTML) 20 Page - Analog Devices |
|
20 / 32 page ![]() ADA4522-1/ADA4522-2/ADA4522-4 Data Sheet Rev. E | Page 20 of 32 TIME (2µs/DIV) VSY = ±2.5V RL = 10kΩ CL = 50pF DUT AV = –1 INPUT OUTPUT +10mV 0 –10mV +1V 0 –1V ERROR BAND POST GAIN = 10 Figure 66. Negative Settling Time to 0.1%, VSY = ±2.5 V TIME (4µs/DIV) VSY = ±15V AND ±27.5V RL = 10kΩ CL = 50pF DUT AV = –1 INPUT OUTPUT +50mV 0 –50mV ERROR BAND POST GAIN = 10 +5V 0 –5V Figure 67. Negative Settling Time to 0.1%, VSY = ±15 V and ±27.5 V 0 10 20 30 40 50 60 100 1k 10k 100k 1M 10M FREQUENCY (Hz) RL = 10kΩ AV = –1 VIN = ±26V VSY = ±27.5V VIN = ±13.5V VSY = ±15V VIN = ±1V VSY = ±2.5V Figure 68. Output Voltage Swing vs. Frequency TIME (2µs/DIV) VSY = ±2.5V RL = 10kΩ CL = 50pF DUT AV = –1 INPUT OUTPUT +10mV 0 –10mV ERROR BAND POST GAIN = 10 +1V 0 –1V Figure 69. Positive Settling Time to 0.1%, VSY = ±2.5 V TIME (4µs/DIV) VSY = ±15V AND ±27.5V RL = 10kΩ CL = 50pF DUT AV = –1 INPUT OUTPUT +50mV 0 –50mV ERROR BAND POST GAIN = 10 +5V 0 –5V Figure 70. Positive Settling Time to 0.1%, VSY = ±15 V and ±27.5 V |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |