AD9528BCPZ datasheet(19/68 Pages) AD

19 / 68 page

AD9528

Data Sheet

Rev. C | Page 18 of 67

No.

Mnemonic

Type1

Description

OUT1

Square Wave Clocking Output 1. High speed output up to 1.25 GHz.

OUT1

Complementary Square Wave Clocking Output 1. High speed output up to 1.25 GHz.

VDD1

3.3 V Supply for the Output 1 Clock Driver.

OUT0

Square Wave Clocking Output 0.

OUT0

Complementary Square Wave Clocking Output 0.

VDD0

3.3 V Supply for the Output 0 Clock Divider.

SYSREF_IN

External SYSREF Input Clock. Along with SYSREF_IN, this pin is the differential input for an external

SYSREF signal. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

SYSREF_IN

Complementary External SYSREF Input Clock. Along with SYSREF_IN, this pin is the differential input

for an external SYSREF signal. Alternatively, this pin can be programmed as a single-ended 3.3 V

CMOS input.

VDD

3.3 V Supply for the PLL1 Input Section.

EP, GND

GND

Exposed Pad. The exposed pad is the ground connection on the chip. It must be soldered to the

analog ground of the printed circuit board (PCB) to ensure proper functionality and heat dissipation,

noise, and mechanical strength benefits.

1 P means power, I means input, O means output, I/O means input/output, P/O means power/output, and GND means ground.

AD9528BCPZ 数据表(PDF) 19 Page - Analog Devices