Data Sheet

ADM7170

Rev. C | Page 17 of 23

APPLICATIONS INFORMATION

ADIsimPOWER DESIGN TOOL

The ADM7170 is supported by the ADIsimPower™ design tool

set. ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic, bill of materials,

and calculate performance in minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and parts count,

taking into consideration the operating conditions and

limitations of the IC and all real external components. For more

information about, and to obtain ADIsimPower design tools,

visit www.analog.com/ADIsimPower.

CAPACITOR SELECTION

Multilayer ceramic capacitors (MLCC) combine small size, low

effective series resistance (ESR), low ESL, and wide operating

temperature range, making them an ideal choice for bypass

capacitors. They are not without limitations, however.

Depending on the dielectric material, the capacitance can vary

dramatically with temperature, dc bias, and ac signal level.

Therefore, selecting the proper capacitor results in the best

circuit performance.

Output Capacitor

The ADM7170 is designed for operation with small, space-

saving ceramic capacitors but functions with most commonly

used capacitors as long as care is taken with regard to the ESR

value. The ESR of the output capacitor affects the stability of the

LDO control loop. A minimum of 4.7 µF capacitance with an

ESR of 0.05 Ω or less is recommended to ensure the stability of the

ADM7170. Transient response to changes in load current is also

affected by output capacitance. Using a larger value of output

capacitance improves the transient response of the ADM7170 to

large changes in load current. Figure 56 shows the transient

responses for an output capacitance value of 4.7 µF.

Input Bypass Capacitor

Connecting a 4.7 µF capacitor from VIN to GND reduces the

circuit sensitivity to PCB layout, especially when long input

traces or a high source impedance is encountered. If greater

than 4.7 µF of output capacitance is required, increase the input

capacitor to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADM7170 if they meet the minimum capacitance and

maximum ESR requirements. Ceramic capacitors are manufac-

tured with a variety of dielectrics, each with different behavior

over temperature and applied voltage. Capacitors require a

dielectric adequate to ensure the minimum capacitance over

the necessary temperature range and dc bias conditions. X5R

or X7R dielectrics with a voltage rating of 6.3 V to 100 V are

recommended. Y5V and Z5U dielectrics are not recommended,

due to their poor temperature and dc bias characteristics.

Figure 57 depicts the capacitance vs. dc bias voltage of a 0805,

4.7 µF, 16 V, X5R capacitor. The voltage stability of a capacitor is

strongly influenced by the capacitor size and voltage rating. In

general, a capacitor in a larger package or higher voltage rating

exhibits better stability. The temperature variation of the X5R

dielectric is ~±15% over the −40°C to +85°C temperature range

and is not a function of package or voltage rating.

Figure 57. Capacitance vs. DC Bias Voltage

Use Equation 1 to determine the worst-case capacitance accounting

for capacitor variation over temperature, component tolerance,

and voltage.

(1)

where:

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

A CH1

160mA

1

2

T

DC BIAS VOLTAGE (V)

20

18

16

14

12

10

8

6

4

2

0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0