Data Sheet

ADM7172

An external capacitor connected to the SS pin determines the

soft start time. The SS pin can be left open for a typical 380 μs

start-up time. Do not ground this pin. When an external soft

start capacitor is used, the soft start time is determined by the

following equation:

where:

TIME (ms)

10

9

8

7

6

5

4

3

2

1

0

0

0.5

1.0

2.0

3.0

3.5

1.5

2.5

1nF

4.7nF

10nF

NOISE REDUCTION OF THE ADM7172 IN

ADJUSTABLE MODE

The ultralow output noise of the ADM7172 is achieved by

keeping the LDO error amplifier in unity gain and setting the

reference voltage equal to the output voltage. This architecture does

not work for an adjustable output voltage LDO in the conventional

sense. However, the ADM7172 architecture allows any fixed

output voltage to be set to a higher voltage with an external voltage

divider. For example, the adjustable (1.2 V in unity gain) output

ADM7172 can be set to a 6 V output according to the following

equation:

The disadvantage of using the ADM7172 in this manner is that

the output voltage noise is proportional to the output voltage.

Therefore, it is best to choose a fixed output voltage that is close

to the target voltage to minimize the increase in output noise.

The adjustable LDO circuit can be modified to reduce the output

voltage noise to levels close to that of the fixed output ADM7172.

The circuit shown in Figure 64 adds two additional components

error amplifier is approximately 0.1 dB to 0.8 dB. The actual

This ensures that the error amplifier always operates at slightly

greater than unity gain.

at a frequency between 0.5 Hz and 10 Hz. This sets the frequency

where the ac gain of the error amplifier is 3 dB less than its dc gain.

VOUT

SENSE

VIN

ADM7172

GND

VIN

VOUT

SS

1nF

4.7µF

4.7µF

1µF

EN

OFF

ON

200kΩ

50kΩ

5kΩ

Figure 64. Noise Reduction Modification

Assuming the noise of a fixed output LDO is approximately

5 μV, identify the noise of the adjustable LDO by using the

following formula:

Based on the component values shown in Figure 64, the

ADM7172 has the following characteristics:

•

DC gain of 5 (14 dB)

•

3 dB roll-off frequency of 0.8 Hz

•

High frequency ac gain of 1.09 (0.75 dB)

•

Noise reduction factor of 4.42 (12.91 dB)

•

RMS noise of the adjustable LDO without noise reduction

of 25 µV rms

•

RMS noise of the adjustable LDO with noise reduction

(assuming 5 µV rms for fixed voltage option) of 5.5 µV rms

EFFECT OF NOISE REDUCTION ON START-UP TIME

The start-up time of the ADM7172 is affected by the noise

reduction network and must be considered in applications

where power supply sequencing is critical.

The noise reduction circuit adds a pole in the feedback loop,

slowing down the start-up time. The start-up time for an

adjustable model with a noise reduction network can be

approximated using the following equation:

as shown in Figure 62, the start-up time is approximately 1.1 sec.

length of the start-up time instead of the soft start capacitor.

Rev. C | Page 19 of 23