ADuM7223CCCZ datasheet(5/17 Pages) AD

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ADuM7223

Data Sheet

Rev. A | Page 4 of 16

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Channel-to-Channel Matching6

tPSKCD

VDD2 = 12 V

8.5

CL = 2 nF

VDD2 = 4.5 V

8.5

CL = 2 nF; A-Grade Only

Output Rise/Fall Time (10% to 90%)

tR/tF

CL = 2 nF, VDD2 = 12 V

Dynamic Input Supply Current per Channel

IDDI(D)

0.05

mA/Mbps

VDD2 = 12 V

Dynamic Output Supply Current per Channel

IDDO(D)

1.65

mA/Mbps

VDD2 = 12 V

Refresh Rate

1.2

Mbps

VDD2 = 12 V

1 Short-circuit duration less than 1 μs. Average power must conform to the limit shown under the Absolute Maximum Ratings.

2 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.

3 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.

4 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is

measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 16 for waveforms of propagation delay parameters.

5 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between ADuM7223 units at the same operating temperature, supply voltages,

and output load within the recommended operating conditions. See Figure 16 for waveforms of propagation delay parameters.

6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier.

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All

minimum/maximum specifications apply over TJ = −40°C to 125°C. All typical specifications are at TA = 25°C, VDD1 = 3.3 V, VDD2 = 12 V.

Switching specifications are tested with CMOS signal levels.

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

DC SPECIFICATIONS

Input Supply Current, Quiescent

IDDI (Q)

0.87

1.4

Output Supply Current per Channel, Quiescent

IDDO (Q)

2.3

3.5

Supply Current at 1 MHz

VDD1 Supply Current

IDD1 (Q)

1.1

1.5

Up to 1 MHz, no load

VDDA/VDDB Supply Current

IDDA(Q), IDDB(Q)

5.6

8.0

Up to 1 MHz, no load

Input Currents

IIA, IIB

−1

+0.01

μA

0 V ≤ VIA, VIB ≤ VDD1

Logic High Input Threshold

VIH

0.7 × VDD1

Logic Low Input Threshold

VIL

0.3 × VDD1

Logic High Output Voltages

VOAH, VOAH

VDD2 − 0.1

VDD2

IOx = −20 mA, VIx = VIxH

Logic Low Output Voltages

VOAL, VOBL

0.0

0.15

IOx = 20 mA, VIx = VIxL

Undervoltage Lockout, VDD1 Supply

Positive Going Threshold

VDD1UV+

2.8

Negative Going Threshold

VDD1UV−

2.6

Hysteresis

VDD1UVH

0.2

Undervoltage Lockout, VDD2 Supply

Positive Going Threshold

VDD2UV+

4.1

4.4

A-Grade

Negative Going Threshold

VDD2UV−

3.2

3.6

A-Grade

Hysteresis

VDD2UVH

0.5

A-Grade

Positive Going Threshold

VDD2UV+

6.9

7.4

B-Grade

Negative Going Threshold

VDD2UV−

5.7

6.2

B-Grade

Hysteresis

VDD2UVH

0.7

B-Grade

Positive Going Threshold

VDD2UV+

10.5

11.2

C-Grade

Negative Going Threshold

VDD2UV−

9.0

9.6

C-Grade

Hysteresis

VDD2UVH

0.9

C-Grade

Output Short-Circuit Pulsed Current1

IOA(SC), IOB(SC)

2.0

4.0

VDD2 = 12 V

Output Source Resistance

ROA, ROB

0.25

0.95

1.5

VDD2 = 12 V, IOx = −250 mA

Output Sink Resistance

ROA, ROB

0.55

0.6

1.35

VDD2 = 12 V, IOx = 250 mA

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