and T_CRIT_A outputs. The fault queue is enabled by set-

ting bit 4 of the Configuration Register high (see Section

1.11).

1.8 INTERNAL REGISTER STRUCTURE

There are four data registers in the LM76, selected by the

Pointer register. At power-up the Pointer is set to “00”; the lo-

cation for the Temperature Register. The Pointer register

latches the last location it was set to. In Interrupt Mode, a

read from the LM76 resets the INT output. Placing the device

in Shutdown mode resets the INT and T_CRIT_A outputs. All

registers are read and write, except the Temperature register

which is read only.

A write to the LM76 will always include the address byte and

the Pointer byte. A write to the Configuration register re-

quires one data byte, while the T

registers require two data bytes.

Reading the LM76 can take place either of two ways: If the

location latched in the Pointer is correct (most of the time it is

expected that the Pointer will point to the Temperature regis-

ter because it will be the data most frequently read from the

LM76), then the read can simply consist of an address byte,

followed by retrieving the corresponding number of data

bytes. If the Pointer needs to be set, then an address byte,

pointer byte, repeat start, and another address byte plus re-

quired number of data bytes will accomplish a read.

The first data byte is the most significant byte with most sig-

nificant bit first, permitting only as much data as necessary to

be read to determine the temperature condition. For in-

stance, if the first four bits of the temperature data indicates

a critical condition, the host processor could immediately

take action to remedy the excessive temperature. At the end

of a read, the LM76 can accept either Acknowledge or No

Acknowledge from the Master (No Acknowledge is typically

used as a signal for the slave that the Master has read its

last byte).

An inadvertent 8-bit read from a 16-bit register, with the D7

bit low, can cause the LM76 to stop in a state where the SDA

line is held low as shown in

Figure 4. This can prevent any

further bus communication until at least 9 additional clock

cycles have occurred. Alternatively, the master can issue

clock cycles until SDA goes high, at which time issuing a

“Stop” condition will reset the LM76.

DS101015-7

DS101015-8

FIGURE 4. Inadvertent 8-Bit Read from 16-Bit Register where D7 is Zero (“0”)

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