LM78 datasheet(3/31 Pages) NSC

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Pin Descriptions

Name(s)

Number

of Pins

Type

Description

IORD

Digital Input

An active low standard ISA bus I/O Read Control.

IOWR

Digital Input

An active low standard ISA bus I/O Write Control.

SYSCLK

Digital Input

The reference clock for the ISA bus. Typically ranges from 4.167 MHz to

8.33 MHz. The minimum clock frequency this input can handle is 1 Hz.

D7–D0

4–11

Digital I/O

Bi-directional ISA bus Data lines. D0 corresponds to the low order bit,

with D7 the high order bit.

CC (+5V)

POWER

+5V V

CC power. Bypass with the parallel combination of 10 µF

(electolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors.

GNDD

GROUND

Internally connected to all digital circuitry.

SMI__IN

Digital Input

Chainable SMI (System Management Interrupt) Input. This is an active

low input that propagates the SMI signal to the SMI output of the LM78

via SMI Mask Register Bit 6 and SMI enable Bit 1 of the Configuration

Chassis

Intrusion

Digital I/O

An active high input from an external circuit which latches a Chassis

Intrusion event. This line can go high without any clamping action

regardless of the powered state of the LM78. The LM78 provides an

internal open drain on this line, controlled by Bit 7 of NMI Mask Register

2, to provide a minimum 20 ms reset of this line.

Power

Switch

Bypass

Digital Output

An active low push-pull output intended to drive an external P-channel

power MOSFET for software power control.

FAN3–FAN1

17–19

Digital Input

0V to +5V amplitude fan tachometer input.

SCL

Digital Input

Serial Bus Clock.

SDA

Digital I/O

Serial Bus bidirectional Data.

RESET

Digital Output

Master Reset, 5 mA driver (open drain), active low output with a 20 ms

minimum pulse width. Available when enabeld via Bit 7 in SMI Mask

NTEST

Test Output

NAND Tree totem-pole output that provides board-level connectivity

testing. Refer to Section 11.0 on NAND Tree testing.

GNDA

GROUND

Internally connected to all analog circuitry. The ground reference for all

analog inputs.

−IN6

Analog Input

Ground-referred inverting op amp input. Refer to Section 4.0, “ANALOG

INPUTS”.

FB6

Analog Output

Output of inverting op amp for Input 6. Refer to section 4.0, “ANALOG

INPUTS”.

FB5

Analog Output

Output of inverting op amp for Input 5. Refer to section 4.0, “ANALOG

INPUTS”.

−IN5

Analog Input

Ground-referred inverting op amp input. Refer to Section 4.0, “ANALOG

INPUTS”.

IN4–IN0

29–33

Analog Input

0V to 4.096V FSR Analog Inputs.

VID3–VID0

34–37

Digital Input

Voltage Supply readouts from P6. This value is read in the VID/Fan

Divisor Register.

BTI

Digital Input

Board Temperature Interrupt driven by O.S. outputs of additional

temperature sensors such as LM75. Provides internal pull-up of 10 k

Ω.

NMI/IRQ

Digital Output

Non-Maskable Interrupt (open source)/Interrupt Request (open drain).

The mode is selected with Bit 5 of the Configuration Register and the

output is enabled when Bit 2 of the Configuration Register is set to 1.

The default state is disabled and IRQ mode.

SMI

Digital Output

System Management Interrupt (open drain). This output is enabled when

Bit 1 in the Configuration Register is set to 1. The default state is

disabled.

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LM78 数据表(PDF) 3 Page - National Semiconductor (TI)

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