UT80C196 datasheet(38/42 Pages) AEROFLEX

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1.26 Reserved Opcode EEH

The industry standard 80C196KD using the MCS-96 ISA

declares the opcode EEH as a reserved opcode and does not

guarantee the generation of the Unimplemented Opcode Inter-

rupt. The UT80CRH196KD, on the other hand, generates the

Unimplemented Opcode Interrupt when the EEH opcode is

executed.

1.27 Byte-Wide Reads of the HSI_Time SFR

In order to ensure that the next HSI event is loaded from the

FIFO into the HSI holding register, the HSI_TIME special

function register must be read as a 16-bit word. Byte-wide

reads of the HSI_TIME register will not result in successful

loading of the HSI holding register.

1.28 BMOV and BMOVI Maximum Count Limitation

The BMOV and BMOVI instructions provide a powerful

method to transferring a large block of data from one location

in memory to another. The syntax for the BMOV and BMOVI

instructions are as follows:

BMOV

SRC_DEST_REG, CNTREG

BMOVI

SRC_DEST_REG, CNTREG

The SRC_DEST_REG is a long register that contains both

addresses for the source and destination blocks. The CNTREG

is a 16-bit register specifying the number of transfers being

performed. Unlike the industry standard 80C196KD which

will accept any 16-bit counter value, the UT80C196KD will

only accept a value in the range of 0000H to 3FFFH.

1.29 BREQ Activation Prior to HLDA

The BREQ signal is used by the UT80C196KD to signal a

DMA arbiter that it would like to recover access to the mem-

ory bus. The UT80C196KD, on the other hand, uses the

HLDA signal to provide confirmation to the DMA arbiter that

the UT80C196KD has relinquished control of the memory

bus. If the wait state control signal (READY) is high when the

UT80C196KD decides it will release the bus based on the

assertion of the HOLD signal, it will drive the BREQ low one

CLKOUT cycle ahead of its assertion of the HLDA. Con-

versely, if the READY signal is low when the UT80C196KD

decides to relinquish the bus, it will assert BREQ coincidently

with HLDA or some CLKOUT cycle later. The latter behavior

is compatible with the industry standard 80C196KD function-

ality, but the former is unique to the UT80C196KD.

1.30 HOLD Must Be Synchronized with CLKOUT

The DMA arbiter must synchronize the HOLD signal with the

CLKOUT on the UT80C196KD. The timing diagram in Fig-

ure 8 eludes to the synchronicity of the HOLD signal, but does

not clearly identify the outcome if the HOLD signal does not

satisfy the timing parameter tHVCH. If the HOLD setup time is

violated on the industry standard 80C196KD, it will require

one additional CLKOUT cycle before it recognizes the state

change of HOLD. Violating the HOLD setup time on the

UT80C196KD will result in a metastable condition and the

UT80C196KD’s reaction is undefined.

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