WM8737L

Preliminary Technical Data

w

AI Rev 3.0 May 2004

26

LEFT CHANNEL

RIGHT CHANNEL

ADCLRC

BCLK

ADCDAT

1/fs

n

3

2

1

n-2

n-1

LSB

MSB

n

3

2

1

n-2

n-1

LSB

MSB

1 BCLK

1 BCLK

Figure 12 I

In DSP mode, the left channel MSB is available on either the 1

(selectable by LRP) following a rising edge of ADCLRC. Right channel data immediately follows left

channel data. Depending on word length, BCLK frequency and sample rate, there may be unused

BCLK cycles between the LSB of the right channel data and the next sample.

Figure 13 DSP Mode Audio Interface

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

1 BCLK

Input Word Length (WL)

1/fs

Figure 14 DSP Mode Audio Interface (mode B, LRP=1)

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master/slave mode are summarised

below. Note that dynamically changing the software format may cause erroneous operation of the

interfaces and is therefore not recommended.

All ADC data is signed 2’s complement. The length of the digital audio data is programmable at

16/20/24 or 32 bits, as shown below. The ADC digital filters process data using 24 bits. If the

WM8737L is programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data. If

the device is programmed to output 32 bits then it packs the LSBs with zeros.