WM8778SEDSSLASHR datasheet(20/50 Pages) WOLFSON

部件名	WM8778SEDS/R

功能描述	24 BIT 192KHZ STEREO CODEC

PDF	50 Pages

Scroll/Zoom	100%

制造商	WOLFSON [Wolfson Microelectronics plc]

网页	http://www.wolfsonmicro.com

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20 / 50 page

WM8778

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PP Rev 1.7 June 2004

The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of

ADCBCLK following a low to high ADCLRC transition and may be sampled on the rising edge of

ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 16)

ADCLRC

ADCBCLK

DOUT

Word Length (WL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

1 BCLK

Figure 16 DSP Early Mode Timing Diagram – ADC Data Output

DSP LATE MODE

In DSP late mode, the MSB of DAC left data is sampled by the WM8778 on the first DACBCLK rising

edge following a DACLRC rising edge. DAC right follow DAC left data (Figure 17).

DACLRC

DACBCLK

DIN

Word Length (WL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

Figure 17 DSP Late Mode Timing Diagram – DAC Data Input

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