LM87 datasheet(9/32 Pages) NSC

9 / 32 page

Functional Description (Continued)

8800 RPM on FAN1 and FAN2. Schmitt-Trigger input cir-

cuitry is included to accommodate slow rise and fall times.

An 8 bit DAC with 0 V to 2.5 V output voltage range can be

used for control of fan speed.

The LM87 has several internal registers, as shown in Figure

4, Table 1. The internal registers and their corresponding

internal LM87 addresses are as follows: and Section 13.0.

These include:

•

Configuration Registers:

Provide control and con-

figuration.

•

Channel Mode Register:

Controls the functionality of

the dual purpose input pins, scaling for internal Vcc mea-

surement, and operation of some IRQ inputs.

•

Interrupt Status Registers:

Two registers to provide

status of each WATCHDOG limit or Interrupt event.

Reading the Status Registers clears any active bits.

•

Interrupt Status Mirror Registers:

Two registers to

provide status of each WATCHDOG limit or Interrupt

event. Reading the Mirror Registers does not affect the

status bits.

•

Interrupt Mask Registers:

Allows masking of indi-

vidual Interrupt sources, as well as separate masking for

each of the two hardware Interrupt outputs.

•

CI Clear Register:

Allows transmitting a 20 ms (mini-

mum) low pulse on the chassis intrusion pin (CI).

•

VID/Fan Divisor Register:

This register contains the

state of the VID0-VID3 input lines and the divisor bits for

FAN1 and FAN2 inputs.

•

VID4 Register:

Contains the state of the VID4 input.

•

Extended Mode Register:

Enable and control the

Alert Response operation.

•

Hardware High Limit Registers:

Registers at 13h,

14h, 17h and 18h where Internal and External ’Hardware’

WATCHDOG temperature high limits are stored. These

limits have Power On Default settings but can be ad-

justed by the user. The values stored at 13h and 14h can

be locked down by setting bits 1 and 2 of Configuration

•

Value and Limit RAM:

The DAC digital output, moni-

toring

results

(temperature,

voltages,

fan

counts),

WATCHDOG limits, and Company/Stepping IDs are all

contained in the Value RAM. The Value RAM consists of

a total of 33 bytes, addresses 19h - 3Fh, containing:

— byte 1 at address 19h contains the DAC Data Regis-

ter

— locations 1Ah and 1Bh contain the WATCHDOG low

limits for AIN1 and AIN2

— locations 1Ch - 1Fh are unassigned and do not have

associated registers

— the next 10 bytes at addresses 20h -29h contain all of

the results

— location 2Ah is unassigned and does not have an

associated register

— the next 18 bytes at addresses 2Bh-3Ch are the

remaining WATCHDOG limits

— the last 2 bytes at addresses 3Eh and 3Fh contain the

Company ID and Stepping ID numbers, respectively

When the LM87 is started, it cycles through each measure-

ment in sequence, and it continuously loops through the

sequence approximately once every 0.4 s. Each measured

value is compared to values stored in WATCHDOG, or Hard-

ware High Limit registers. When the measured value violates

the programmed limit the LM87 will set a corresponding

Interrupt in the Interrupt Status Registers. The hardware

Interrupt line INT# is fully programmable with separate

masking of each Interrupt source. In addition, the Configu-

ration Register has a control bit to enable or disable the

hardware Interrupt. Another hardware Interrupt line avail-

able, THERM# is used to signal temperature specific events.

Having a dedicated interrupt for these conditions allows

specific actions to be taken for thermal events. This output is

enabled by setting bit 2 of Configuration Register 1.

The Chassis Intrusion input is designed to accept an active

high signal from an external circuit that activates and latches

when the case is removed from the computer.

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