ADA4860-1

Rev. 0 | Page 17 of 20

LAYOUT AND CIRCUIT BOARD PARASITICS

Careful attention to printed circuit board (PCB) layout prevents

associated board parasitics from becoming problematic and

affecting gain flatness and −3 dB bandwidth. In the printed

circuit environment, parasitics around the summing junction

(inverting input) or output pins can alter pulse and frequency

response. Parasitic capacitance can be unintentionally created

on a PC board via two parallel metal planes with a small vertical

separation (in FR4). To avoid parasitic problems near the

summing junction, signal line connections between the

feedback and gain resistors should be kept as short as possible

to minimize the inductance and stray capacitance. For similar

reasons, termination and load resistors should be located as

close as possible to the respective inputs. Removing the ground

plane on all layers from the area near and under the input and

output pins reduces stray capacitance.

In a second test, 5.6 pF of capacitance was added directly at the

output of the gain = +2 amplifier. Figure 61 shows the results.

Extra output capacitive loading on the ADA4860-1 also causes

bandwidth extensions, as seen in Figure 61. The effect on the

gain = +2 circuit is more pronounced with lighter resistive

loading (1 kΩ). For pulse response behavior with added output

capacitances, see Figure 23, Figure 24, Figure 26, Figure 27,

Figure 29, Figure 30, Figure 32, and Figure 33.

3

–6

–5

–4

–3

–2

–1

1

2

0

1

100

10

1000

FREQUENCY (MHz)

G = +2

To illustrate the affects of parasitic capacitance, a small

capacitor of 0.4 pF from the amplifiers summing junction

(inverting input) to ground was intentionally added. This was

done on two boards with equal and opposite gains of +2 and −2.

Figure 60 reveals the effects of parasitic capacitance at the

summing junction for both noninverting and inverting gain

circuits. With gain = +2, the additional 0.4 pF of added

capacitance created an extra 43% −3 dB bandwidth extension,

plus some extra peaking. For gain = −2, a 5% increase in −3 dB

bandwidth was created with an extra 0.4 pF on summing

junction.

Figure 61. Small Signal Frequency Response vs. Output Capacitive Load

For more information on high speed board layout, go to:

www.analog.com and

www.analog.com/library/analogDialogue/archives/39-

09/layout.html.

1

–6

–5

–4

–3

–2

–1

0

1

100

10

1000

FREQUENCY (MHz)

Figure 60. Small Signal Frequency Response vs.

Added Summing Junction Capacitance