2

Third party brands and names are the property of their respective owners.

Integrated

Circuit

Systems, Inc.

ICS952004

Pin Description

The ICS952004 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets.When used with a zero delay buffer

such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks signals for such a

system.

The ICS952004 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the first

to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the use of a

serially programmable I

ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output

clock.TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system

conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.

General Description

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1, 11, 13, 19, 29,

42, 48

VDD

PWR

Power supply for 3.3V

FS0

IN

Frequency select pin.

REF0

OUT

14.318 MHz reference clock.

FS1

IN

Frequency select pin.

REF1

OUT

14.318 MHz reference clock.

FS2

IN

Frequency select pin.

REF2

OUT

14.318 MHz reference clock.

5, 8, 18, 24, 25,

32, 37, 41, 46

GND

PWR

Ground pin for 3V outputs.

6

X1

IN

Crystal input,nominally 14.318MHz.

7

X2

OUT

Crystal output, nominally 14.318MHz.

10, 9

ZCLK(1:0)

OUT

Hyperzip clock outputs.

12

PCI_STOP#

IN

Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when

MODE pin is in Mobile mode

FS3

IN

Frequency select pin.

PCICLK_F0

OUT

PCI clock output, not affected by PCI_STOP#

FS4

IN

Frequency select pin.

PCICLK_F1

OUT

PCI clock output, not affected by PCI_STOP#

23, 22, 21, 20, 17,

16

PCICLK (5:0)

OUT

PCI clock outputs.

MULTISEL

IN

3.3V LVTTL input for selecting the current multiplier for CPU outputs.

24_48MHz

OUT

Clock output for super I/O/USB default is 24MHz

27

48MHz

OUT

48MHz output clock

28, 36

AVDD

PWR

Analog power supply 3.3V

30, 31

AGPCLK (1:0)

OUT

AGP outputs defined as 2X PCI. These may not be stopped.

PD#

IN

Asynchronous active low input pin used to power down the device into a

low power state. The internal clocks are disabled and the VCO and the

crystal are stopped. The latency of the power down will not be greater

than 3ms.

Vtt_PWRGD

IN

This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal.

When Vtt_PWRGD goes high the frequency select will be latched at

power on thereafter the pin is an asynchronous active low power down

pin.

34

SDATA

I/O

Data pin for I

35

SCLK

IN

Clock pin of I

38

I REF

OUT

This pin establishes the reference current for the CPUCLK

pairs. This pin requires a fixed precision resistor tied to ground

in order to establish the appropriate current.

43, 39

CPUCLKC (1:0)

OUT

"Complementary" clocks of differential pair CPU outputs. These clocks

are 180° out of phase with SDRAM clocks. These open drain outputs

need an external 1.5V pull-up.

44, 40

CPUCLKT (1:0)

OUT

"True" clocks of differential pair CPU outputs. These clocks are in phase

with SDRAM clocks. These open drain outputs need an external 1.5V pull-

up.

45

CPU_STOP#

IN

Stops all CPUCLKs clocks at logic 0 level, when MODE pin is in Mobile

mode

47

SDRAM

OUT

SDRAM clock output.

15

26

33

2

3

4

14