2

Integrated

Circuit

Systems, Inc.

ICS952621

0756A—09/10/04

Pin Description

PIN

#

PIN NAME

PIN TYPE

DESCRIPTION

1

FS_A/REF1

I/O

FS_A latched input for frequency select

Reference output, 14.318Hz

2

FS_B/REF0

I/O

FS_B latched input for frequency select

Reference output, 14.318Hz

3

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

4

X1

IN

Crystal input, Nominally 14.318MHz.

5

X2

OUT

Crystal output, Nominally 14.318MHz

6

GND

PWR

Ground pin.

7

PCICLK_F0

OUT

Free running PCI clock not affected by PCI_STOP# .

8

PCICLK_F1

OUT

Free running PCI clock not affected by PCI_STOP# .

9

PCICLK_F2

OUT

Free running PCI clock not affected by PCI_STOP# .

10

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

11

GND

PWR

Ground pin.

12

PCICLK0

OUT

PCI clock output.

13

PCICLK1

OUT

PCI clock output.

14

PCICLK2

OUT

PCI clock output.

15

PCICLK3

OUT

PCI clock output.

16

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

17

GND

PWR

Ground pin.

18

PCICLK4

OUT

PCI clock output.

19

PCICLK5

OUT

PCI clock output.

20

PD#

IN

Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used

to power down the device. The internal clocks are disabled and the VCO and

the crystal are stopped.

21

48MHz_DOT

OUT

48.008MHz Dot clock output

22

48MHz_USB

OUT

48.008MHz USB clock output

23

GND

PWR

Ground pin.

24

VDD48

PWR

Power for 48MHz output buffers and fixed PLL core.

25

3V66_3/VCH

OUT

3.3V 66.66MHz clock output

VCH: 48MHz VCH clock output

26

3V66_2

OUT

3.3V 66.66MHz clock output

27

VDD3V66

PWR

Power pin for the 3V66 clocks.

28

GND

PWR

Ground pin.

29

3V66_1

OUT

3.3V 66.66MHz clock output

30

3V66_0

OUT

3.3V 66.66MHz clock output

31

SCLK

IN

Clock pin of SMBus circuitry, 5V tolerant.

32

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

33

VttPWR_GD#

IN

This 3.3V LVTTL input is a level sensitive strobe used to determine when latch

inputs are valid and are ready to be sampled. This is an active low input.

34

VDD

OUT

Power supply, nominal 3.3V

35

SRCCLKC

OUT

Complementary clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

36

SRCCLKT

OUT

True clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

37

GND

PWR

Ground pin.

38

CPUCLKC0

OUT

Complementary clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

39

CPUCLKT0

OUT

True clock of differential pair CPU outputs. These are current mode outputs.

External resistors are required for voltage bias.

40

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

41

CPUCLKC1

OUT

Complementary clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

42

CPUCLKT1

OUT

True clock of differential pair CPU outputs. These are current mode outputs.

External resistors are required for voltage bias.

43

GND

PWR

Ground pin.

44

CPUCLKC_ITP

OUT

"Complementary" clocks of differential pair CPU outputs for ITP.. These are

current mode outputs. External resistors are required for voltage bias.

45

CPUCLKT_ITP

OUT

"True" clocks of differential pair CPU outputs for ITP. These are current mode

outputs. External resistors are required for voltage bias.

46

IREF

OUT

This pin establishes the reference current for the differential current-mode

output pairs. This pin requires a fixed precision resistor tied to ground in order

to establish the appropriate current. 475 ohms is the standard value.

47

GND

PWR

Ground pin.

48

VDDA

PWR

3.3V power for the PLL core.