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IP_TNETV1050 数据表(PDF) 3 Page - Texas Instruments |
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IP_TNETV1050 数据表(HTML) 3 Page - Texas Instruments |
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3 / 5 page  Description The TNETV1050 is a communica- tions processor based on a MIPS32 Reduced Instruction Set Computer (RISC) processor along with a C55x DSP. This device has a rich peripheral set architected specifically for VoIP Phone applications, which reduces the bill of materials cost, time, and complexity to develop an IP Phone. The TNETV1050 combines the key processor, communication, and peripheral functions necessary to build a basic or advanced IP phone. The TNETV1050 architecture uses advanced design features to provide flexibility and performance throughput, while conserving power consumption. Combined with Telogy Software for IP Phone applications, the TNETV1050 provides a complete hardware/software solution capable of reducing system design cycle times. The RISC processor supplies the overall system services and performs user interface, network management, protocol stack management, call processing, and task scheduling functions. The DSP processor provides real-time voice processing functions such as echo cancellation, compression, PCM processing, and tone genera- tion/detection. IP phone designs are simplified through on-chip peripherals such as a 16-bit color LCD controller, 8x8 keypad interface, USB 1.1 controller (Host or Device), UART serial interface, programmable serial port, two VLYNQ interfaces, and several general purpose I/O. The integrated dual-channel 16-bit CODEC includes the critical functions needed for IP Phone applications, including two ADCs (with five programmable inputs) and two DACs (with four programmable outputs). Other codec features include analog and digital sidetone control, anti-aliasing filter, programmable gain options, and programmable sampling rate (8 or 16 ksps). 32-bit RISC Processor Memory Configuration • 16K-Byte 4-way set associative Instruction-Cache • 16K-Byte 4-way set associative Data-Cache • Programmable Memory Management Unit (MMU) • 4K-Byte RAM on chip • 4K-Byte ROM on chip, with boot code Digital Signal Processor (DSP) Memory Configuration • 12K-Word 2-way set associative Instruction-Cache • 64K-Word RAM on chip: - 32K-Word dual access - 32K-Word single access • Universal 4-channel DMA controller • Dedicated peripheral DMA controller External Memory Interface Supporting • 2 SDRAM Chip Selects providing 128M-Byte • 3 Chip Selects providing 16M-Byte each, RAM or ROM • 1 Chip Select providing 32M-Byte, FLASH Overall • 324-Ball PBGA (Plastic Ball Grid Array) package • 3.3V I/O Supply Voltage • 1.5V Core Supply Voltage, integrated Voltage Regulator • Reduced power modes available Telephony Interface McBSP McBSP VLYNQ™ 5 Pin Codec 2 Channel Serial UART GPIO Keypad 8x8 Clock/Power Manager DSP DMA Ethernet Switch 3 port MAC Ethernet PHY Voltage Regulator TMS320C55x™ DSP MIPS R4000 TNETV1050 IP Phone Processor VLYNQ™ 3 Pin USB 1.1 Host USB 1.1 Device LCD Controller External Memory Interface Ethernet PHY MAC DMA 3 |
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