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THC63LVDR84C 数据表(PDF) 10 Page - THine Electronics, Inc. |
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THC63LVDR84C 数据表(HTML) 10 Page - THine Electronics, Inc. |
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10 / 16 page ![]() THC63LVDR84C_Rev.1.20_E Copyright©2016 THine Electronics, Inc. 9 THine Electronics, Inc. Security E Input to Output Delay RCLK+ Vdiff = 0V VCC/2 tRCD CLKOUT Note:Vdiff=(RCLK+)-(RCLK-) Figure 10.Input Clock to Output Clock Delay Time Phase Lock Loop Set Time VCC33 3.0V RCLK+/- /PDWN VCC/2 CLKOUT VCC/2 tRPLL Figure 11. PLL Lock Loop Set Time |
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