M2082 datasheet(6/14 Pages) ICST

6 / 14 page

M2080/81/82 M2085/86/87 Datasheet Rev 0.4

6 of 14

Revised 30Jul2004

I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0

Integrated

Circuit

Systems, Inc.

M2080/81/82, M2085/86/87

VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN

Preliminar y In f o r m atio n

The relationship between the nominal VCSO center

frequency (Fvcso), the Mfin divider, the Mfec divider,

the Rfec divider, and the input reference frequency (Fin)

is:

The Mfec, Rfec, and Mfin dividers can be set by pin

configuration using the input pins FEC_SEL1, FEC_SEL0,

FIN_SEL1,

and FIN_SEL0.

Post-PLL Divider

The M2080/81/82 and M2085/86/87 also feature a

post-PLL (P) divider.

Through use of the P divider, the device’s output

frequency (Fout) can be that of the VCSO (such as

622.08MHz

) or the VCSO frequency divided by 4, 8 or 32

(common optical reference clocks in SONET and SDH

systems).

The P_SEL2:0 pins select the value for the P divider. (See

Table 8 on pg. 4.)

Accounting for the P divider, the complete relationship

between the input clock reference frequency (Fin) and

output clock frequency (Fout) is defined as:

Due to the narrow tuning range of the VCSO (+120ppm

guaranteed), appropriate selection of all of the following

are required for the PLL be able to lock: VCSO center

frequency, input frequency, and divider selections.

TriState

The TriState feature puts the LVPECL output driver into

a high impedance state, effectively disconnecting the

driver from the FOUT and nFOUT pins of the device. In

TriState, the M208x Series is not driving the output

clock net with a defined logic level. The impedance of

the clock net is then set to 50

Ω by the external circuit

resistors. The 50

Ω impedance level of the LVPECL

TriState allows manufacturing In-circuit Test to drive the

clock net with an external LVPECL source to validate

the integrity of clock net and the clock load.

Any unused output (single-ended or differential) should

be left unconnected (floating) in system application.

This minimizes output switching current and therefore

minimizes noise modulation of the VCSO.

Loss of Lock Indicator (LOL) Output Pin

Under normal device operation, when the PLL is locked,

the LOL Phase Detector drives LOL to logic 0. Under

circumstances when the VCSO cannot fully phase lock

to the input (as measured by a greater than 4 ns

discrepancy between the feedback and reference clock

rising edges at the LOL Phase Detector) the LOL output

goes to logic 1. The LOL pin will return back to logic 0

when the phase detector error is less than 2 ns. The

loss of lock indicator is a low current LVCMOS output.

Guidelines for Using LOL

In a given application, the magnitude of peak-to-peak

jitter at the phase detector will usually increase as the

Rfec divider is increased. If the LOL pin will be used to

detect an unusual clock condition, or a clock fault, the

FEC_SEL1:0

pins should be set to provide a phase

detector frequency of 5MHz or greater (the phase

detector frequency is equal to Fin divided by the Rfec

divider). Otherwise, false LOL indications may result. A

phase detector frequency of 10MHz or greater is

desirable when reference jitter is over 500ps, or when

the device is used within a noisy system environment.

LOL

should not be used when the device is used in a

loop timing application.

Fvcso

Fin

Mfin

Mfec

Rfec

--------------

Fout

Fvcso

-------------------

Fin

Mfin

fec

Rfec

----------------------------------

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