M2080/81/82 M2085/86/87 Datasheet Rev 0.4

4 of 14

Revised 30Jul2004

Integrated

Circuit

Systems, Inc.

M2080/81/82, M2085/86/87

Preliminar y In f o r m atio n

M2082/87: FEC De-map LUT, Both OTU1 and OTU2

Use this option for both OTU1 or OTU2 de-mapping

applications. The Mfec divider value is kept nearly

constant to maintain similar loop bandwidth using one

set of external filter component values.

P Divider Look-Up Table (LUT)

also available, plus a TriState mode. The output can be

placed into the valid states as listed in Table 8.

General Guidelines for Phase Detector Frequency

The phase detector frequency (Fpd) is equal to the

input reference frequency (Fref) divided by the Rfec

divider value, or:

Fpd = Fref / Rfec

loop timing applications to assure PLL tracking,

especially during GR-253 jitter tolerance testing. The

recommended maximum phase detector frequency

the phase detector frequency should be 5MHz or

overly sensitive, and higher phase detector

should not be used during loop timing mode.

output for clock fault detection.

The M208x Series is a PLL (Phase Locked Loop) based

clock generator that generates output clocks synchro-

nized to one of two selectable input reference clocks.

An internal high "Q" SAW delay line provides low jitter

signal performance and establishes the output

frequency of the VCSO (Voltage Controlled SAW

Oscillator). In a given M208x Series device, the VCSO

center frequency is fixed. A common center frequency

applications. The VCSO center frequency is specified at

time of order (see “Ordering Information” on pg. 14).

The VCSO has a guaranteed tuning range of

±120 ppm

(commercial temperature grade).

Pin selectable dividers are used within the PLL and

for the output clock. This enables tailoring of device

functionality and performance. The FEC feedback and

reference dividers (the “Mfec Divider” and “Rfec

Divider”) provide the multiplication ratios necessary to

accomodate clock translation for both forward and

inverse Forward Error Correction. The Mfec and Rfec

dividers also control the phase detector frequency. The

feedback divider (labeled “Mfin Divider”) provides the

broader division options needed to accomodate various

reference clock frequencies.

Information”

frequency:

(OTU2)

reference clock to be the base input frequency

77.76

pg. 3.)

The P divider scales the VCSO output enabling lower

output frequency selections (Table 8).

FEC_SEL1:0

1

0

Mfec Rfec

Description

Base Input

Rate (MHz)

Fvcso =

Base Output

Rate (MHz)

For M2082 or M2087 with Fvcso = 622.08 (OTU1 or OTU2 FEC rate):

0

0

622.08

0

1

622.08

622.08

1

0

622.08

1

1

622.08

622.08

Table 7: M2082/87: FEC De-map LUT, Both OTU1 and OTU2

P_SEL2:0

P Value

M2080-622.0800 or M2085-622.0800

Output Frequency (MHz)

0

0

0

32

19.44

0

0

1

32

19.44

0

1

0

1

622.08

0

1

1

4

155.52

1

0

0

8

77.76

1

0

1

4

155.52

1

1

0

8

77.76

1

1

1

TriState

N/A

Table 8: P Divider Look-Up Table (LUT)

Key to Device Variants and Look-up Table Options

Device

Variant

Look-up Table Option

Mfin Lookup Table is:

Mfec Look-up Table is:

M2080

Table 3

(includes divider value 32)

Table 5 (FEC mapper LUT)

M2081

Table 6 (FEC de-mapper LUT)

M2082

Table 7 (FEC de-mapper LUT)

M2085

Table 4

(includes divider value 16)

Table 5 (FEC mapper LUT)

M2086

Table 6 (FEC de-mapper LUT)

M2087

Table 7 (FEC de-mapper LUT)

Table 9: Key to Device Variants and Look-up Table Options