M2087 datasheet(3/14 Pages) ICST

3 / 14 page

M2080/81/82 Datasheet Rev 0.4

3 of 14

Revised 30Jul2004

Integr ated Circuit Systems , Inc. ● Netw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (5 08) 85 2-54 00

M2080/81/82, M2085/86/87

VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN

Preliminar y In f o r m atio n

Integrated

Circuit

Systems, Inc.

DETAILED BLOCK DIAGRAM

Figure 3: Detailed Block Diagram

DIVIDER SELECTION TABLES

Mfin Divider Look-Up Tables (LUT)

The FIN_SEL1:0 pins select the feedback divider value

(“Mfin”), which sets the overall PLL ratio range. Since

the VCSO frequency is fixed, this allows input reference

selection. The look-up tables vary by device variant.

M2080/81/82: Mfin Value LUT (Includes Divide by 32)

M2085/86/87: Mfin Value LUT (Includes Divide by 16)

Mfec and Rfec Divider Look-Up Tables (LUTs)

The FEC_SEL pins select the Mfec/Rfec divider ratio. The

look-up tables vary by device variant. The Mfec and

Rfec values also establish phase detector frequency.

A lower phase detector frequency improves jitter

tolerance and lowers loop bandwidth.

M2080/85: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)

M2081/86: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)

Use this option for either OTU1 or OTU2 de-mapping

applications, but not both.

Phase

Locked

Loop

(PLL)

M2080 Series

SAW Delay Line

Phase

Shifter

VCSO

POST

nVC

POST

nOP_OUT

OP_OUT

POST

LOOP

OP_IN

nOP_IN

PLL

Phase

Detector

Loop Filter

Amplifier

External

Loop Filter

Components

FEC_SEL1:0

FIN_SEL1:0

Rfec

Div

MUX

REF_SEL

DIF_REF0

nDIF_REF0

Mfin Divider

LUT

Mfin Divider

(1, 4, 8, 32) or

(1, 4, 8, 16)

Mfec Div

NBW

Mfec / Rfec

Divider LUT

DIF_REF1

nDIF_REF1

Auto

Ref Sel

LOL

Phase

Detector

REF_ACK

AUTO

LOL

FOUT

nFOUT

CML or PECL

Options

P Divider

(1, 4, 8, 32,

or TriState)

P_SEL2:0

P Divider

LUT

FIN_SEL1:0

Mfin

Value

Sample Input Reference Freq. (MHz) Options

For M20801, M2081 & M20822

Note 1: For M2080 with Fvcso = 666.5143 or 669.3266

Note 2: For M2081 and M2082 with Fvcso = 622.0800.

0 0

19.44

0 1

77.76

155.52

622.08

Table 3: M2080/81/82: Mfin Value LUT (Includes Divide by 32)

FIN_SEL1:0

Mfin

Value

Sample Input Reference Freq. (MHz) Options

For M20851, M2086 & M20872

Note 1: For M2085 with Fvcso = 666.5143 or 669.3266

Note 2: For M2086 and M2087 with Fvcso = 622.0800.

0 0

38.88

0 1

77.76

155.52

622.08

Table 4: M2085/86/87: Mfin Value LUT (Includes Divide by 16)

FEC_SEL1:0

Mfec Rfec

Description

Base Input

Rate (MHz)

Fvcso =

Base Output

Rate (MHz)

For M2080 or M2085 with Fvcso = 666.5143 (OTU1 FEC rate):

15 14 255/238 OC-48 to OTU1 encode

622.08

666.5143

15 15 OTU1 repeater or jitter attenuator

666.5143 666.5143

For M2080 or M2085 with Fvcso = 669.3266 (OTU2 FEC rate):

85 79 255/237 OC-192 to OTU2 encode

622.08

669.3266

85 85 OTU2 repeater or jitter attenuator

669.3266 669.3266

Table 5: M2080/85: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)

FEC_SEL1:0

Mfec Rfec

Description

Base Input

Rate (MHz)

Fvcso =

Base Output

Rate (MHz)

For M2081 or M2086 with Fvcso = 622.08 (OTU1 or OTU2 FEC rate):

79 85 237/255 OTU2 to OC-192 decode 669.3266

622.08

79 79 OC-192 repeater or jitter attenuator

622.08

14 15 238/255 OTU1 to OC-48 decode 666.5143

622.08

14 14 OC-48 repeater or jitter attenuator

622.08

Table 6: M2081/86: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)

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