STK17TA8-R45I datasheet(14/22 Pages) ETC

14 / 22 page

STK17TA8

February 2004

Document Control # ML0023 rev 0.3

is enabled.

CALIBRATING THE CLOCK

The RTC is driven by a quartz controlled oscillator

with a nominal frequency of 32.768 KHz. Clock

accuracy will depend on the quality of the crystal,

usually specified to 35 ppm limits at 25

°C. This error

could equate to + 1.53 minutes per month. The

STK17TA8 employs a calibration circuit that can

improve the accuracy to + 1/-2 ppm at 25

°C. The

calibration circuit adds or subtracts counts from the

oscillator divider circuit.

The number of times pulses are suppressed (sub-

tracted, negative calibration) or split (added, positive

calibration) depends upon the value loaded into the

five calibration bits found in control register 1FFF8h.

Adding counts speeds the clock up; subtracting

counts slows the clock down. The Calibration bits

occupy the the five lower order bits in the control

value between 0 and 31 in binary form. Bit D5 is a

Sign bit, where a “1” indicates positive calibration

and a “0” indicates negative calibration. Calibration

occurs within a 64 minute cycle. The first 62 minutes

in the cycle may, once per minute, have one second

either shortened by 128 or lengthened by 256 oscil-

lator cycles.

If a binary “1” is loaded into the register, only the first

2 minutes of the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected, and

so on. Therefore each calibration step has the effect

of adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles. That is

+4.068 or -2.034 ppm of adjustment per calibration

step in the calibration register.

In order to determine how to set the calibration one

may set the CAL bit in register 1FFF0h to 1, which

causes the INT pin to toggle at a nominal 512 Hz.

Any deviation measured from the 512 Hz will indi-

cate the degree and direction of the required correc-

tion. For example, a reading of 512.010124 Hz

would indicate a +20 ppm error, requiring a -10

(001010) to be loaded into the Calibration register.

Note that setting or changing the calibration register

does not affect the frequency test output frequency.

ALARM

The alarm function compares user-programmed val-

ues to the corresponding time-of-day values. When

a match occurs, the alarm event occurs. The alarm

drives an internal flag, AF, and may drive the INT pin

if desired.

There are four alarm match fields. They are date,

hours, minutes and seconds. Each of these fields

also has a Match bit that is used to determine if the

field is used in the alarm match logic. Setting the

Match bit to “0” indicates that the corresponding field

will be used in the match process.

Depending on the Match bits, the alarm can occur

as specifically as one particular second on one day

of the month, or as frequently as once per second

continuously. The MSB of each alarm register is a

Match bit. Selecting none of the Match bits (all 1’s)

indicates that no match is required. The alarm

occurs every second. Setting the match select bit for

seconds to “0” causes the logic to match the sec-

onds alarm value to the current time of day. Since a

match will occur for only one value per minute, the

alarm occurs once per minute. Likewise, setting the

seconds and minutes Match bits causes an exact

match of these values. Thus, an alarm will occur

once per hour. Setting seconds, minutes and hours

causes a match once per day. Lastly, selecting all

match values causes an exact time and date match.

Selecting other bit combinations will not produce

meaningful results, however the alarm circuit should

follow the functions described.

There are two ways a user can detect an alarm

event, by reading the AF flag or monitoring the INT

pin. The AF flag in the register 1FFF0h will indicate

that a date/time match has occurred. The AF bit will

be set to 1 when a match occurs. Reading the

Flags/Control register clears the alarm flag bit (and

all others). A hardware interrupt pin may also be

used to detect an alarm event.

WATCHDOG TIMER

The watchdog timer is a free running down counter

that uses the 32 Hz clock (31.25 ms) derived from

the crystal oscillator. The oscillator must be running

for the watchdog to function. It begins counting

down from the value loaded in the Watchdog Timer

The counter consists of a loadable register and a

free running counter. On power up, the watchdog

timeout value in register 1FFF7h is loaded into the

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