LMC6484AMJSLASH883 datasheet(12/22 Pages) NSC

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Typical Performance Characteristics V

S = +15V, Single Supply, TA = 25˚C unless otherwise

specified (Continued)

Application Information

1.0 Amplifier Topology

The

LMC6484

incorporates

specially

designed

wide-compliance range current mirrors and the body effect to

extend input common mode range to each supply rail.

Complementary paralleled differential input stages, like the

type used in other CMOS and bipolar rail-to-rail input ampli-

fiers, were not used because of their inherent accuracy prob-

lems due to CMRR, cross-over distortion, and open-loop

gain variation.

The LMC6484’s input stage design is complemented by an

output stage capable of rail-to-rail output swing even when

driving a large load. Rail-to-rail output swing is obtained by

taking the output directly from the internal integrator instead

of an output buffer stage.

2.0 Input Common-Mode Voltage Range

Unlike Bi-FET amplifier designs, the LMC6484 does not ex-

hibit phase inversion when an input voltage exceeds the

negative supply voltage.

Figure 1 shows an input voltage ex-

ceeding both supplies with no resulting phase inversion on

the output.

The absolute maximum input voltage is 300 mV beyond ei-

ther supply rail at room temperature. Voltages greatly ex-

ceeding this absolute maximum rating, as in

Figure 2, can

cause excessive current to flow in or out of the input pins

possibly affecting reliability.

Applications that exceed this rating must externally limit the

maximum input current to ±5 mA with an input resistor as

shown in

Figure 3.

3.0 Rail-To-Rail Output

The approximated output resistance of the LMC6484 is

180

Ω sourcing and 130Ω sinking at V

S = 3V and 110Ω

sourcing and 83

Ω sinking at V

S = 5V. Using the calculated

output resistance, maximum output voltage swing can be es-

timated as a function of load.

4.0 Capacitive Load Tolerance

The LMC6484 can typically directly drive a 100 pF load with

S = 15V at unity gain without oscillating. The unity gain fol-

lower is the most sensitive configuration. Direct capacitive

Stability vs

Capacitive Load

DS011714-89

Stability vs

Capacitive Load

DS011714-90

DS011714-10

FIGURE 1. An Input Voltage Signal Exceeds the

LMC6484 Power Supply Voltages with

No Output Phase Inversion

DS011714-12

FIGURE 2. A ±7.5V Input Signal Greatly

Exceeds the 3V Supply in

Figure 3 Causing

No Phase Inversion Due to R

DS011714-11

FIGURE 3. R

I Input Current Protection for

Voltages Exceeding the Supply Voltage

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