LATCH-UP

In the past, most CMOS IC’s were susceptible to a damaging

phenomena known as latch-up. This occurred when an ESD

current spike or other large signal was applied to any of the

pins of an IC. The LMC7215 and LMC7225 both are de-

signed to make them highly resistant to this type of damage.

They have passed qualification tests with input currents on

any lead up to 300 mA at temperatures up to 125˚C.

SPICE MODELS

For a SPICE model of the LMC7215, LMC7225 and many

other op-amps and comparators, contact the NSC Customer

Response Center at 800-272-9959 or on the World Wide

Web at http://www.national.com/models/index.html.

SOT-23-5 Tape and Reel Specification

REEL DIMENSIONS

DS012853-8

FIGURE 5. R

DS012853-9

FIGURE 6.

DS012853-10

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