CS5540-AS datasheet(10/22 Pages) CIRRUS

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CS5540

DS503PP1

2. GENERAL DESCRIPTION

The CS5540 is a low-power and low-voltage 24-bit

∆−Σ analog-to-digital converter (ADC). It is opti-

mized to convert analog signals in DC measure-

ment applications such as temperature and pressure

measurement, and various portable devices where

low power consumption is required.

To accommodate these applications, the ADC inte-

grates analog input and reference buffers for in-

creased

input

impedance

and

includes

two-channel multiplexer. Absolute accuracy is ac-

complished via self-calibration. The device also

operates with a variety of supply configurations

while drawing a nominal 330 µA.

The CS5540 includes a digital filter which achieves

simultaneous rejection of 50/60 Hz and provides

single conversion settling at a 6.7 SPS throughput.

The filter’s output word rate can be increased by

approximately 1.22X by using a 40 kHz master

clock, although the 50/60 Hz rejection will be sac-

rificed.

To ease communications between the ADC and a

microcontroller, the converter includes a simple

three-wire serial interface which is SPI and Mi-

crowire compatible. A Schmitt Trigger input is pro-

vided on the serial clock (SCLK) input.

2.1 Analog Input

Figure 3 illustrates a block diagram of the CS5540.

The device consists of a multiplexer, a unity gain

coarse/fine charge input buffer, a fourth order

∆−Σ

modulator, and a digital filter.

2.1.1 Analog Input Model

Figure 4 illustrates the input models for the AIN

pins. The model includes a coarse/fine charge buff-

er which reduces the dynamic current demands

from the analog input signal. The buffer is designed

to accommodate rail to rail (common-mode plus

signal) input voltages. Typical CVF (sampling)

current is about 8 nA (MCLK = 32.768 kHz). Ap-

plication Note 30, “Switched-Capacitor A/D Input

Structures”, details various input architectures.

VREF+

Sinc

Digital

Filter

AIN2+

AIN2-

AIN1+

AIN1-

VREF-

Differential

Order

∆Σ

Modulator

Serial

Port

SDO

SCLK

CHS

Figure 3. Multiplexer Configuration

AIN

C = 8 pF

f = 2*MCLK = 65.536 kHz

φ Coarse

φ Fine

n = CV osf

os ≤ 25mV

Figure 4. Input model for AIN+ and AIN- pins

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