2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

Igt (Tj)

Fig. 5: Relative variation of gate trigger current

and holding current versus junction temperature.

-40 -20

0

60

80 100 120 140

Igt (Tj = 25 ºC)

Ih (Tj)

Ih (Tj = 25 ºC)

40

20

Tj (ºC)

Ih

Igt

1.00

0.10

0.01

K=[Zth(j-a) / Rth(j-a)]

Fig. 4-2: Relative variation of thermal

impedance junction to ambient versus pulse

duration. (recommended pad layout)

1E-2

1E-1

1E+0

1E+1

1E+2

5E+2

tp (s)

Tamb (ºC)

FS04...D

SURFACE MOUNT SCR

0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.5

1

1.5

P (W)

Fig. 1: Maximum average power dissipation

versus average on-state current

0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

25

50

100

125

P (W)

Fig. 2: Correlation between maximum average power dissipation and

maximum allowable temperatures (Tamb and T case) for different

thermal resistances heatsink+contact.

T case (ºC)

125

Fig. 3: Average and DC on-state current versus

ambient temperature (device mounted on FR4

with recommended pad layout)

Jun- 02

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

I T(AV) (A)

0

25

100

125

50

75

2

2.5

3

Tamb (ºC)

IT(AV)(A)

3.5

α

360 º

75

120

115

Rth= 37C/W

Rth= 15C/W

Rth= 10C/W

Rth= 0C/W

Rth= 5C/W

α=180º

α = 180 º

DC

1.0

0.5

0.2

0.1

K=[Zth(j-c) / Rth(j-c)]

Fig. 4-1: Relative variation of thermal

impedance junction to case versus pulse

duration.

1E-3

1E-2

1E-1

1E+0

tp (s)

α = 80 º