RT9264CS datasheet(5/8 Pages) ETC

5 / 8 page

Preliminary

RT9264

DS9264-00 December 2001

www.richtek-ic.com.tw

Application Note

Output Voltage Setting

Referring to application circuits Fig.1 to Fig.3, the

output voltage of the switching regulator (VOUT1) can

be set with Eq.1.

The LDO output voltage can be set with Eq.2.

Layout Guide

• A full GND plane without gap break.

• VOUT1 to GND noise bypass – Short and wide

connection for C2 to Pin1 and Pin6.

• VIN to GND noise bypass – Add a 100µF capacitor

close to L1 inductor, when VIN is not an idea

voltage source.

• Minimized FB/LFB node copper area and keep far

away from noise sources.

• Minimized parasitic capacitance connecting to LX

and EXT nodes, which may cause additional

switching loss.

• The following diagram is an example of 2-layer

board layout for application circuits Fig.1 and

Fig.2.

First Layer

Second Layer (Full GND Plane)

RT9264

)

(

OUT

Eq.1

)

(

OUT

Eq.2

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