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MM5483MS 数据表(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 MM5483MS
功能描述  MM5483 Liquid Crystal Display Driver
PDF  6 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

MM5483MS 数据表(HTML) 2 Page - National Semiconductor (TI)

  MM5483MS Datasheet HTML 1Page - National Semiconductor (TI) MM5483MS Datasheet HTML 2Page - National Semiconductor (TI) MM5483MS Datasheet HTML 3Page - National Semiconductor (TI) MM5483MS Datasheet HTML 4Page - National Semiconductor (TI) MM5483MS Datasheet HTML 5Page - National Semiconductor (TI) MM5483MS Datasheet HTML 6Page - National Semiconductor (TI)  
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Absolute Maximum Ratings
If MilitaryAerospace specified devices are required
please contact the National Semiconductor Sales
OfficeDistributors for availability and specifications
Voltage at Any Pin
VSS to VSS a 10V
Operating Temperature
b
40 Cto a85 C
Storage Temperature
b
65 Cto a150 C
Power Dissipation
300 mW at a85 C
350 mW at a25 C
Junction Temperature
a
150 C
Lead Temperature
(Soldering 10 seconds)
300 C
DC Electrical Characteristics
TA within operating range VDD e 30V to 10V VSS e 0V unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Power Supply
30
10
V
Power Supply Current
R e 1M C e 470 pF
Outputs Open
VDD e 30V
9
15
m
A
VDD e 50V
17
25
m
A
VDD e 100V
35
45
m
A
OSC e 0V Outputs Open
BPIN e 32 Hz VDD e 30V
15
25
m
A
Input Voltage Levels
Load Clock Data
Logic ‘‘0’’
VDD e 50V
09
V
Logic ‘‘1’’
VDD e 50V
24
V
Logic ‘‘0’’
VDD e 30V
04
V
Logic ‘‘1’’
VDD e 30V
20
V
Output Current Levels
Segments and Data Out
Sink
VDD e 30V VOUT e 03V
20
m
A
Source
VDD e 30V VOUT e 27V
20
m
A
BP OUT
Sink
VDD e 30V VOUT e 03V
320
m
A
Source
VDD e 30V VOUT e 27V
320
m
A
AC Electrical Characteristics VDD t 47V VSS e 0V unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
fC
Clock Frequency VDD e 3V
500
kHz
tCH
Clock Period High
(Notes 1 2)
500
ns
tCL
Clock Period Low
500
ns
tDS
Data Set-Up before Clock
300
ns
tDH
Data Hold Time after Clock
100
ns
tLW
Minimum Load Pulse Width
500
ns
tLTC
Load to Clock
400
ns
tCDO
Clock to Data Valid
400
750
ns
Note 1
AC input waveform specification for test purpose tr s 20 ns tf s 20 ns f e 500 kHz 50% g10% duty cycle
Note 2
Clock input rise and fall times must not exceed 300 ns
Note 3
Output offset voltage is g50 mV with CSEGMENT e 250 pF CBP e 8750 pF
Functional Description
A block diagram for the MM5483 is shown in
Figure 1 and a
package pinout is shown in
Figure 2 Figure 3 shows a pos-
sible 3-wire connection system with a typical signal format
for
Figure 3 Shown in Figure 4 the load input is an asyn-
chronous input and lets data through from the shift register
to the output buffers any time it is high The load input can
be connected to VDD for 2-wire control as shown in Figure
5 In the 2-wire control mode 31 bits (or less depending on
the number of segments used) of data are clocked into the
MM5483 in a short time frame (with less than 01 second
there probably will be no noticeable flicker) with no more
clocks until new information is to be displayed If data was
slowly clocked in it can be seen to ‘‘walk’’ across the dis-
play in the 2-wire mode An AC timing diagram can be seen
in
Figure 6 It should be noted that data out is not a TTL-
compatible output
2



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